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...need. I haven't pasted the regalloc debug info here because it is quite huge, but if you tell me what specific details you need I will include them. Thanks for your help! 2012/7/14 Jakob Stoklund Olesen <stoklund at 2pi.dk> > > On Jul 14, 2012, at 10:09 AM, Borja Ferrer <borja.ferav at gmail.com> wrote: > > > Hello, > > > > I'm getting a machine verifier error after introducing the earlyclobber > constraint to some instructions where the src and dest regs can't be the > same. The offending instruction pattern is this one: > > > &g...

Hello Jakob, Did you get a chance to take a look into this, and if not, can you do it when you get some spare time? Thanks! 2012/12/19 Borja Ferrer <borja.ferav at gmail.com> > We did something like this back when the register allocator couldn't split >> live ranges. >> > > Yes, I remember the isWinToJoinCrossClass() function, removed here: > > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.c...

Jakob, one more hint, I've placed some asserts around the code you added and noticed that the InlineSpiller::insertReload() function is not being called. 2012/7/14 Borja Ferrer <borja.ferav at gmail.com> > Hello Jakob, > > I'm still getting the error, I can give you any other debug info you need. > I haven't pasted the regalloc debug info here because it is quite huge, but > if you tell me what specific details you need I will include them. > > Thanks...

On Jan 7, 2013, at 4:58 AM, Borja Ferrer <borja.ferav at gmail.com> wrote: > Hello Jakob, > > Did you get a chance to take a look into this, and if not, can you do it when you get some spare time? It's not likely I'll have time to look at this in the near future. I'd recommend you do it yourself. /jakob > 2012/12/19 Bo...

...meantime, I can live with this workaround until an official fix is implemented. I'll fill in a bug report to track this problem so you can take a look at it when appropiate. 2013/1/7 Jakob Stoklund Olesen <stoklund at 2pi.dk> > > On Jan 7, 2013, at 4:58 AM, Borja Ferrer <borja.ferav at gmail.com> wrote: > > Hello Jakob, > > Did you get a chance to take a look into this, and if not, can you do it > when you get some spare time? > > > It's not likely I'll have time to look at this in the near future. I'd > recommend you do it yourself. &...

On Jul 15, 2012, at 9:20 AM, Borja Ferrer <borja.ferav at gmail.com> wrote: > Jakob, one more hint, I've placed some asserts around the code you added and noticed that the InlineSpiller::insertReload() function is not being called. > > 2012/7/14 Borja Ferrer <borja.ferav at gmail.com> > Hello Jakob, > > I'm still g...

Hello everybody, During the past week I've kept looking for a solution to this but i couldn't find one, is there really a way to get this type of information or some workaround? Thanks. 2010/12/22 Borja Ferrer <borja.ferav at gmail.com> > Hello, > > Is there a way to determine before register allocation if a virtual reg is > mapped to the lo or hi part of a piece of a value? Basically i need to tell > the register allocator to use a certain set of registers for the lo part and > others for the h...

Hello, Is there a way to determine before register allocation if a virtual reg is mapped to the lo or hi part of a piece of a value? Basically i need to tell the register allocator to use a certain set of registers for the lo part and others for the hi part, so in order to do this i would have to know if the data value was expanded into smaller pieces and which piece is each one. Additionally,

On Jan 9, 2013, at 10:46 AM, Borja Ferrer <borja.ferav at gmail.com> wrote: > Ok, I've found that marking tiny live intervals as not spillable inside VirtRegAuxInfo::CalculateWeightAndHint is not playing nicely with very constrained regclasses, in my case a regclass composed of only one register. > As a workaround, instead of marking the...

On Jul 14, 2012, at 10:09 AM, Borja Ferrer <borja.ferav at gmail.com> wrote: > Hello, > > I'm getting a machine verifier error after introducing the earlyclobber constraint to some instructions where the src and dest regs can't be the same. The offending instruction pattern is this one: > > let canFoldAsLoad = 1, > isReMa...

On Dec 19, 2012, at 8:58 AM, Borja Ferrer <borja.ferav at gmail.com> wrote: > Hello Jakob, > > I think I've found something interesting that may help you get a better idea of what's going on. > > While looking at the debug info I noticed that the coalescer was removing lots of copies that could help the allocator make more...

Hello, I'm getting a machine verifier error after introducing the earlyclobber constraint to some instructions where the src and dest regs can't be the same. The offending instruction pattern is this one: let canFoldAsLoad = 1, isReMaterializable = 1, Constraints = "@earlyclobber $dst" in def LDDWRdPtrQ : Inst<(outs DREGS:$dst), (ins memri:$src),

...he regalloc. Obviously the generated code is not optimal at all, because there are many useless copies around. I'm pretty sure this is not the right fix at all, but it can give you a hint incase the problem is in the coalescer and not in the regalloc. Thanks! 2012/12/18 Borja Ferrer <borja.ferav at gmail.com> > Hello Jakob, > > >> Those are some severe constraints on register allocation, but it ought to >> be possible anyway. >> > > Indeed, these constraints aren't playing very well with the register > allocator :\ > > >> >> You...

Hello, while testing trivial functions in my backend i noticed a suboptimal way of assigning regs that had the following pattern, consider the following function: typedef unsigned short t; t foo(t a, t b) { t a4 = b^a^18; return a4; } Argument "a" is passed in R15:R14 and argument "b" is passed in R13:R12, the return value is stored in R15:R14. Producing the

Hello Jakob, > Those are some severe constraints on register allocation, but it ought to > be possible anyway. > Indeed, these constraints aren't playing very well with the register allocator :\ > > You may wan't to investigate how RAGreedy::canEvictInterference() is > behaving. > Ok, this is what I've noticed, not sure if it makes sense at all but, regalloc

...per-register with the 8bit as the sub. At least for my allocator, this will simplify writing the algorithm without changing the mechanics. I wonder, how many other targets have sub-registers larger than super-registers? Thanks, Jeff Kunkel On Sun, Aug 29, 2010 at 12:04 PM, Borja Ferrer <borja.ferav at gmail.com>wrote: > Hello everbody, > > This is my first email to the list, and hope to write more as i get more > involved in LLVM. I'm currently writing a backend for a 8 bit > microcontroller, and i have arrived to a point where i need to take a design > decision in o...

Hello, I'm adding a new function attribute in clang and llvm for a backend I'm writing that treats prolog and epilogue code in a special way inside interrupt handlers, similar to what naked does. One way I've seen to do this is to add a new attribute type in Attributes.h, however to me it feels bad to add a target dependent attribute into this place which is very target independent.

On Jul 15, 2012, at 4:50 PM, Borja Ferrer <borja.ferav at gmail.com> wrote: > I think I'm getting a bit closer to the problem. I've found that the call to InlineSpiller::foldMemoryOperand() inside InlineSpiller::spillAroundUses() is causing the problems. > As a test, I removed that call and with your yesterday's patch I'm not...

> > We did something like this back when the register allocator couldn't split > live ranges. > Yes, I remember the isWinToJoinCrossClass() function, removed here: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?r1=152016&r2=155551&diff_format=h that prevented some coalescing to the cost of leaving many unnecessary copies around for very

Hello, I would like to reserve a register or make it available to the register allocator depending if the stack is used inside a function or not. By using the stack i mean the following: if all regs are spilled so that frame space has to be allocated, arguments passed through the stack and allocas. I know how to get the last two options when the register allocator is run since that info is