I've been working on adding support for the PPC 440/450 "embedded" cores to the PowerPC backend. These are used on IBM's Blue Gene L and P supercomputers, but are also used in other environments (like on the Xilinx Virtex-5). Here is my first patch. I'm new to LLVM, and so I apologize if this is the wrong way to do this [the online docs seem to imply that a patch should be sent to a mailing list, although does not specify which one, should it go to the bug tracker instead?]. I've tried to touch as little of the existing code as possible. There are some other changes which should probably be made, but would require touching the existing PowerPC code. For example, the general load/store itinerary should really be split into a general load and general store. Also, on the so-called "Book E" embedded PPC cores, the sync instruction is called msync (same opcode, different name). I'm not sure what the best way of doing a predicate-base asm name is. I'm just about done with a patch to add support for the FP2 (aka Double Hummer) v2f64 vector instruction set, but I figured that it would be good to make that a separate patch. Thanks in advance, Hal -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm_ppc440_20111004.diff Type: text/x-patch Size: 32133 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20111005/09a167db/attachment.bin>
On Oct 5, 2011, at 8:22 AM, Hal Finkel wrote:> I've been working on adding support for the PPC 440/450 "embedded" cores > to the PowerPC backend. These are used on IBM's Blue Gene L and P > supercomputers, but are also used in other environments (like on the > Xilinx Virtex-5). Here is my first patch. I'm new to LLVM, and so I > apologize if this is the wrong way to do this [the online docs seem to > imply that a patch should be sent to a mailing list, although does not > specify which one, should it go to the bug tracker instead?].llvm-commits is the place to send your patches.> I've tried to touch as little of the existing code as possible. There > are some other changes which should probably be made, but would require > touching the existing PowerPC code.This patch looks fine to me, but I am missing some test cases. There should at least be a test case just sending some code through this scheduler.> For example, the general load/store > itinerary should really be split into a general load and general store. > Also, on the so-called "Book E" embedded PPC cores, the sync instruction > is called msync (same opcode, different name). I'm not sure what the > best way of doing a predicate-base asm name is.I am not sure how to do that. X86 has alternative syntaxes, but that is way overkill.> I'm just about done with a patch to add support for the FP2 (aka Double > Hummer) v2f64 vector instruction set, but I figured that it would be > good to make that a separate patch.Definitely. /jakob
On Oct 5, 2011, at 2:14 PM, Jakob Stoklund Olesen wrote:> > On Oct 5, 2011, at 8:22 AM, Hal Finkel wrote: > >> I've been working on adding support for the PPC 440/450 "embedded" cores >> to the PowerPC backend. These are used on IBM's Blue Gene L and P >> supercomputers, but are also used in other environments (like on the >> Xilinx Virtex-5). Here is my first patch. I'm new to LLVM, and so I >> apologize if this is the wrong way to do this [the online docs seem to >> imply that a patch should be sent to a mailing list, although does not >> specify which one, should it go to the bug tracker instead?]. > > llvm-commits is the place to send your patches. > >> I've tried to touch as little of the existing code as possible. There >> are some other changes which should probably be made, but would require >> touching the existing PowerPC code. > > This patch looks fine to me, but I am missing some test cases. > > There should at least be a test case just sending some code through this scheduler. > >> For example, the general load/store >> itinerary should really be split into a general load and general store. >> Also, on the so-called "Book E" embedded PPC cores, the sync instruction >> is called msync (same opcode, different name). I'm not sure what the >> best way of doing a predicate-base asm name is. > > I am not sure how to do that. X86 has alternative syntaxes, but that is way overkill.You can put a predicate on an InstAlias or a MnemonicAlias. Just do: def : MnemonicAlias<"msync", "sync">, Requires<[IsBookE]>;> >> I'm just about done with a patch to add support for the FP2 (aka Double >> Hummer) v2f64 vector instruction set, but I figured that it would be >> good to make that a separate patch. > > Definitely. > > /jakob > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
I've attached the latest version of my patch to support the PPC 440/450 cores in the PowerPC backend. I've also included a small patch to clang so that it will recognize -target-cpu 440 and pass that through to the code generator (and assembler). Thanks in advance, Hal On Wed, 2011-10-05 at 14:14 -0700, Jakob Stoklund Olesen wrote:> On Oct 5, 2011, at 8:22 AM, Hal Finkel wrote: > > > I've been working on adding support for the PPC 440/450 "embedded" cores > > to the PowerPC backend. These are used on IBM's Blue Gene L and P > > supercomputers, but are also used in other environments (like on the > > Xilinx Virtex-5). Here is my first patch. I'm new to LLVM, and so I > > apologize if this is the wrong way to do this [the online docs seem to > > imply that a patch should be sent to a mailing list, although does not > > specify which one, should it go to the bug tracker instead?]. > > llvm-commits is the place to send your patches. > > > I've tried to touch as little of the existing code as possible. There > > are some other changes which should probably be made, but would require > > touching the existing PowerPC code. > > This patch looks fine to me, but I am missing some test cases. > > There should at least be a test case just sending some code through this scheduler. > > > For example, the general load/store > > itinerary should really be split into a general load and general store. > > Also, on the so-called "Book E" embedded PPC cores, the sync instruction > > is called msync (same opcode, different name). I'm not sure what the > > best way of doing a predicate-base asm name is. > > I am not sure how to do that. X86 has alternative syntaxes, but that is way overkill. > > > I'm just about done with a patch to add support for the FP2 (aka Double > > Hummer) v2f64 vector instruction set, but I figured that it would be > > good to make that a separate patch. > > Definitely. > > /jakob >-- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm_ppc440-20111010.diff Type: text/x-patch Size: 41791 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20111010/a1ad0a68/attachment.bin> -------------- next part -------------- A non-text attachment was scrubbed... Name: clang_ppc440-20111010.diff Type: text/x-patch Size: 3057 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20111010/a1ad0a68/attachment-0001.bin>