search for: mnemonicalias

Hello! I have a question about Instructions and MnemonicAliases. Let's say I have an instruction (an instruction prefix actually, in the X86 backend), and the instruction has 'Defs' and 'Uses' defined for it. If I define a MnemonicAlias from that instruction prefix to another, then do the 'Defs' and 'Uses' get "applie...

Short answer: No, that's not how assembly aliases work. A MnemonicAlias is entirely a construct of the assembly parser. By the time anything that matches via the alias gets to parts of the toolchain that know anything about uses and defs, it's as-if there only ever were one instruction definition at all. -Jim On Mar 25, 2013, at 10:08 AM, Muhammad Tauqir Ahmad &l...

I am new to the LLVM backends, I am wondering how instruction selection is done in LLVM backends, I looked at the .td files in Target/X86, they all seem to be small and do not deal with common X86 instructions, i.e. mov, push, pop, etc. Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Oct 5, 2011, at 8:22 AM, Hal Finkel wrote: > I've been working on adding support for the PPC 440/450 "embedded" cores > to the PowerPC backend. These are used on IBM's Blue Gene L and P > supercomputers, but are also used in other environments (like on the > Xilinx Virtex-5). Here is my first patch. I'm new to LLVM, and so I > apologize if this is the wrong

I've been working on adding support for the PPC 440/450 "embedded" cores to the PowerPC backend. These are used on IBM's Blue Gene L and P supercomputers, but are also used in other environments (like on the Xilinx Virtex-5). Here is my first patch. I'm new to LLVM, and so I apologize if this is the wrong way to do this [the online docs seem to imply that a patch should be