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...on was my starting point). It turns out that current DFAPacketizer is using itineraries, but my schedule is based on SchedMachineModel (I was recommended to use it since the itineraries are being phased out). I was wondering if there is an automated tool that would convert from SchedMcahineModel to Itinerary based mode? As far as I understand they both convey the same information so there should be a way to convert between them. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20151106/d7df74f1/attachment.html>

> On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > > What is the best way to model a scheduler for a VLIW in-order architecture? > I’ve looked at the Hexagon and R600 architectures and they are using itineraries. I wanted to understand the benefit in using itineraries over the per operand scheduling. > > I

Hi, What is the best way to model a scheduler for a VLIW in-order architecture? I've looked at the Hexagon and R600 architectures and they are using itineraries. I wanted to understand the benefit in using itineraries over the per operand scheduling. I also found this thread from almost 2 years ago: http://lists.llvm.org/pipermail/llvm-dev/2016-April/098763.html At that time it seemed the

...pass. // This is overriden by OperandCycles if the // Itineraries are queried instead. let MispredictPenalty = 8; // Based on estimate of pipeline depth. let Itineraries = CortexA9Itineraries; // FIXME: Many vector operations were never given an itinerary. We // haven't mapped these to the new model either. let CompleteModel = 0; } I'm guessing this is probably the way forward for my case since Itineraries seem to be already mostly defined. Phil On Wed, Apr 20, 2016 at 1:27 PM, Phil Tomson <phil.a.tomson at gmail.com<mailto:phil...

...oint). It turns out that current DFAPacketizer is using > itineraries, but my schedule is based on SchedMachineModel (I was > recommended to use it since the itineraries are being phased out). I > was wondering if there is an automated tool that would convert from > SchedMcahineModel to Itinerary based mode? As far as I understand > they both convey the same information so there should be a way to > convert between them. > > -- > > > > > Rail Shafigulin > Software Engineer > Esencia Technologies > > > _________________________________________...

Hello Andy, I want to use the existing scheduling models to estimate performance on a subtarget. For that, I am looking at the new llvm-mca tool where they only use SchedReadWrite and state that not supporting Instruction Itineraries is a limitation. I have also read that the Instruction Itineraries allow to model certain things which cannot be represented in the SchedReadWrite however, I am

...vailable on this topic, I even asked on the IRC channel and nobody seems to know how it is done, since everyone is moving towards the SchedMachineModel. Not many people work with either the machine model or itineraries. Be careful! I think the DFAPacketizer will only be effective on a very simple itinerary (which could easily have been expressed in the new machine model instead). I’ve heard stories of it “blowing up” on large itineraries. I have no direct experience with it. > 2. Write a new packetizer which will use the SchedMachineModel, however, as I said before, I have a very limited experien...

All, I am working on a scheduler for X86 and would like to include instruction latencies. It appears that this information is gathered from instruction itineraries, but that there isn't an itinerary for X86. I also can't seem to find documentation on how to add this for X86. Any pointers would be helpfull. Aran -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 194 bytes Desc: This is a digitally sign...

Hi Krzysztof, 2018-02-08 13:32 GMT+08:00 Andrew Trick via llvm-dev < llvm-dev at lists.llvm.org>: > > > On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Hi, > > What is the best way to model a scheduler for a VLIW in-order architecture? > I’ve looked at the Hexagon and R600 architectures and they are using

So if I use the SchedMachineModel method, can I just skip itineraries? Phil On Wed, Apr 20, 2016 at 12:29 PM, Sergei Larin <slarin at codeaurora.org> wrote: > Target does make a difference. VLIW needs more hand-holding. For what you > are describing it should be fairly simple. > > > > Best strategy – see what other targets do. ARM might be a good start for > generic

Is there a way to express a multiple pipeline itinerary using the current scheme (maybe some trick with setting NextCycles = 0)? Specifically, consider a case where a floating-point load simultaneously uses units from a floating-point pipeline and a load/store pipeline. Thanks in advance, Hal -- Hal Finkel Postdoctoral Appointee Leadership Computing...

> On Mar 26, 2018, at 5:18 AM, Pedro Lopes via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > > From what I can understand from analyzing several *.td files, there are two ways of specifying scheduling information for a specific target, either using SchedWriteRes and InstrItinClass/Data. > > Specifically looking at ARMScheduleA9.td, I can find both

We have a two different dimensions for each instruction: slot assignments, and operand timings. These two are unrelated to each other, and also each (or both) can change for any given instruction from one architecture version to the next. The main concern for us was which of these mechanisms contains all the information that we need. We cannot express all the scheduling details by hand, and

Hi, >From what I can understand from analyzing several *.td files, there are two ways of specifying scheduling information for a specific target, either using SchedWriteRes and InstrItinClass/Data. Specifically looking at ARMScheduleA9.td, I can find both representations and a comment (in the beggining of the file): // This section contains legacy support for itineraries. This is // required

...ead_me) fence 2 load r1, r2, 0, 32 bitop1 r509, r510, 0, OR, 64 load r510, r509, 0, 64 addI r509, r509, 16, 64 jabs r511 the movimm which sets up the address for the load has been moved up prior to the fence. Is there a way to indicate in the itinerary that position of the fence should be fixed - no instruction reordering "through" the fence/barrier? Phil -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160822/d5c1bf32/attachment.html>

...;> I tried setting >> let mayLoad = 1 { >> class InstrLD .... { >> } >> } >> >> But that didn't seem to work. When I looked at the debug output the >> latency for the load instruction was set to 1. >> >> However when I changed load itinerary description in the schedule to >> >> def MyTargetItineraries : >> .............. >> InstrItinData<LD, [InstrStage<2, [BranchSlot, NonBranchSlot], 1>]>, >> .............. >> >> That seem to produce correct latency in the debug outp...

Hello Hal. > Is there a way to express a multiple pipeline itinerary using the > current scheme Yes, surely > (maybe some trick with setting NextCycles = 0)? Yep! > Specifically, consider a case where a floating-point load simultaneously > uses units from a floating-point pipeline and a load/store pipeline. Look into ARM itineraries, they contain a dec...

...r510, 0, OR, 64 > > load r510, r509, 0, 64 > > addI r509, r509, 16, 64 > > jabs r511 > > > > the movimm which sets up the address for the load has been moved up > prior to the fence. > > > > Is there a way to indicate in the itinerary that position of the fence > should be fixed - no instruction reordering "through" the fence/barrier? > > > > Phil > > _______________________________________________ > > LLVM Developers mailing list > > llvm-dev at lists.llvm.org > > http://lists.ll...

...I realizing my initial simple understanding of instruction itineraries may be completely off. I'm trying to model a CPU that has a latency of 2 cycles for multiplications fully pipelined (so it can start a new one after one cycle) First of all, is there a document that describes the instruction itinerary model in some detail ? For example looking at MBlaze target MBlaeSchedule.td I can see something like MblazeSchedule.td ... def IIImul : InstrItinClass; ... InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>, Does that mean Mul's are expected to have a...

Hello, Is there code in place for lowering the bitcode SSA into an optimized sequence for the itineraries? I have been curious whether or not such descriptions exist for the x86 family or whether there are techniques to make a clear determination of this information. Regards, Carter. -------------- next part -------------- An HTML attachment was scrubbed... URL: