Displaying 5 results from an estimated 5 matches for "mnemonicalia".
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mnemonicalias
2013 Mar 25
2
[LLVMdev] MnemonicAliases and side-effects
Hello!
I have a question about Instructions and MnemonicAliases.
Let's say I have an instruction (an instruction prefix actually, in
the X86 backend), and the instruction has 'Defs' and 'Uses' defined
for it.
If I define a MnemonicAlias from that instruction prefix to another,
then do the 'Defs' and 'Uses' get "appli...
2013 Mar 25
0
[LLVMdev] MnemonicAliases and side-effects
Short answer: No, that's not how assembly aliases work.
A MnemonicAlias is entirely a construct of the assembly parser. By the time anything that matches via the alias gets to parts of the toolchain that know anything about uses and defs, it's as-if there only ever were one instruction definition at all.
-Jim
On Mar 25, 2013, at 10:08 AM, Muhammad Tauqir Ahmad &...
2011 Sep 30
2
[LLVMdev] LLVM backends instruction selection
I am new to the LLVM backends, I am wondering how instruction selection is
done in LLVM backends, I looked at the .td files in Target/X86, they all
seem to be small and do not deal with common X86 instructions, i.e. mov,
push, pop, etc.
Thanks
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2011 Oct 05
0
[LLVMdev] Support for PPC 440/450
On Oct 5, 2011, at 8:22 AM, Hal Finkel wrote:
> I've been working on adding support for the PPC 440/450 "embedded" cores
> to the PowerPC backend. These are used on IBM's Blue Gene L and P
> supercomputers, but are also used in other environments (like on the
> Xilinx Virtex-5). Here is my first patch. I'm new to LLVM, and so I
> apologize if this is the wrong
2011 Oct 05
3
[LLVMdev] Support for PPC 440/450
I've been working on adding support for the PPC 440/450 "embedded" cores
to the PowerPC backend. These are used on IBM's Blue Gene L and P
supercomputers, but are also used in other environments (like on the
Xilinx Virtex-5). Here is my first patch. I'm new to LLVM, and so I
apologize if this is the wrong way to do this [the online docs seem to
imply that a patch should be