search for: itinerari

Is there a way to convert between SchedMachineModel and Itineraries? I was trying to write a very simple VLIW packetizer (Hexagon was my starting point). It turns out that current DFAPacketizer is using itineraries, but my schedule is based on SchedMachineModel (I was recommended to use it since the itineraries are being phased out). I was wondering if there is...

> On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > > What is the best way to model a scheduler for a VLIW in-order architecture? > I’ve looked at the Hexagon and R600 architectures and they are using itineraries. I wanted to understand the benefit in using itineraries over the per operand scheduling. > > I also found this thread from almost 2 years ago: > http://lists.llvm.org/pipermail/llvm-dev/2016-April/098763.html <http://lists.llvm.org/pipermail/llvm-dev/2016-April/098763.html> >...

Hi, What is the best way to model a scheduler for a VLIW in-order architecture? I've looked at the Hexagon and R600 architectures and they are using itineraries. I wanted to understand the benefit in using itineraries over the per operand scheduling. I also found this thread from almost 2 years ago: http://lists.llvm.org/pipermail/llvm-dev/2016-April/098763.html At that time it seemed the itineraries are a better choice, but is it still the case? Also,...

Hi Phil. You more or less answered your own question, but let me give you some more info. Maybe it is of use. >From what I understand the SchedMachineModel is the future, although it is not as powerful as itineraries at present. The mi-scheduler is mostly developed around out-of-orders cores, I believe (I love to hear arguments on the contrary). Some of the constraints that can be found in in-order micro architectures cannot be expressed in the per-operand scheduling model and the heuristics of the pre-RA sch...

...Message ----- > From: "Rail Shafigulin via llvm-dev" <llvm-dev at lists.llvm.org> > To: "llvm-dev" <llvm-dev at lists.llvm.org> > Sent: Monday, November 9, 2015 10:09:07 AM > Subject: Re: [llvm-dev] Is there a way to convert between SchedMachineModel and Itineraries? > > > Anybody? Does anyone at all know how to do it? There is no direct conversion. Although they are similar models, they are different. The strength of Itineraries lies in modeling pipelines with complex hazards (especially those that are not fully pipelined, or have other similar...

Hello Andy, I want to use the existing scheduling models to estimate performance on a subtarget. For that, I am looking at the new llvm-mca tool where they only use SchedReadWrite and state that not supporting Instruction Itineraries is a limitation. I have also read that the Instruction Itineraries allow to model certain things which cannot be represented in the SchedReadWrite however, I am still trying to find out what and I cannot find any information on this subject. I was under the impression that, in some cases, Instr...

...;mailto:llvm-dev at lists.llvm.org>> > > To: "llvm-dev" <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> > > Sent: Monday, November 9, 2015 10:09:07 AM > > Subject: Re: [llvm-dev] Is there a way to convert between SchedMachineModel and Itineraries? > > > > > > Anybody? Does anyone at all know how to do it? > > There is no direct conversion. Although they are similar models, they are different. The strength of Itineraries lies in modeling pipelines with complex hazards (especially those that are not fully pipelined,...

All, I am working on a scheduler for X86 and would like to include instruction latencies. It appears that this information is gathered from instruction itineraries, but that there isn't an itinerary for X86. I also can't seem to find documentation on how to add this for X86. Any pointers would be helpfull. Aran -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size...

...> > > On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Hi, > > What is the best way to model a scheduler for a VLIW in-order architecture? > I’ve looked at the Hexagon and R600 architectures and they are using > itineraries. I wanted to understand the benefit in using itineraries over > the per operand scheduling. > > ​Do you have time to give comment on why Hexagon still use itineraries, rather than switching to per operand scheduling like ARM does? I really like to hear your opinion. Thanks.​ :-) -- We...

So if I use the SchedMachineModel method, can I just skip itineraries? Phil On Wed, Apr 20, 2016 at 12:29 PM, Sergei Larin <slarin at codeaurora.org> wrote: > Target does make a difference. VLIW needs more hand-holding. For what you > are describing it should be fairly simple. > > > > Best strategy – see what other targets do. ARM might b...

Is there a way to express a multiple pipeline itinerary using the current scheme (maybe some trick with setting NextCycles = 0)? Specifically, consider a case where a floating-point load simultaneously uses units from a floating-point pipeline and a load/store pipeline. Thanks in advance, Hal -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory

...s of specifying scheduling information for a specific target, either using SchedWriteRes and InstrItinClass/Data. > > Specifically looking at ARMScheduleA9.td, I can find both representations and a comment (in the beggining of the file): > > // This section contains legacy support for itineraries. This is > // required until SD and PostRA schedulers are replaced by MachineScheduler. > > This poses several question as to: > 1) which representation gives the better cost estimation? > 2) AFAIK, MachineScheduler can also take advantage from InstrItineraries with the Scoreboard...

...main concern for us was which of these mechanisms contains all the information that we need. We cannot express all the scheduling details by hand, and majority of it was auto-generated anyway. I don't know if the new model has all the required pieces of information, but we've been using itineraries for a while, and we stuck with them. The short answer is "because it works", but it's not meant to imply that nothing else would. -Krzysztof On 2/8/2018 8:49 AM, 陳韋任 wrote: > Hi Krzysztof, > > 2018-02-08 13:32 GMT+08:00 Andrew Trick via llvm-dev > <llvm-dev at...

...s, there are two ways of specifying scheduling information for a specific target, either using SchedWriteRes and InstrItinClass/Data. Specifically looking at ARMScheduleA9.td, I can find both representations and a comment (in the beggining of the file): // This section contains legacy support for itineraries. This is // required until SD and PostRA schedulers are replaced by MachineScheduler. This poses several question as to: 1) which representation gives the better cost estimation? 2) AFAIK, MachineScheduler can also take advantage from InstrItineraries with the ScoreboardHazardRecognizer for bett...

We improved our instruction itineraries and now we're seeing our testcases for fence instructions break. For example, we have this testcase: @write_me = external global i32 @read_me = external global i32 ; Function Attrs: nounwind define i32 @xstg_intrinsic(i32 %foo) #0 { entry: ; CHECK: store r0, r1, 0, 32 ; CHECK-NEXT:...

...rLD .... { >> } >> } >> >> But that didn't seem to work. When I looked at the debug output the >> latency for the load instruction was set to 1. >> >> However when I changed load itinerary description in the schedule to >> >> def MyTargetItineraries : >> .............. >> InstrItinData<LD, [InstrStage<2, [BranchSlot, NonBranchSlot], 1>]>, >> .............. >> >> That seem to produce correct latency in the debug output. >> >> Do you know what could be the problem? Am I missi...

...s a multiple pipeline itinerary using the > current scheme Yes, surely > (maybe some trick with setting NextCycles = 0)? Yep! > Specifically, consider a case where a floating-point load simultaneously > uses units from a floating-point pipeline and a load/store pipeline. Look into ARM itineraries, they contain a decent amount of such examples. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

On Mon, Aug 22, 2016 at 11:40 AM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > > On Aug 22, 2016, at 11:20, Phil Tomson via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > We improved our instruction itineraries and now we're seeing our > testcases for fence instructions break. > > > > For example, we have this testcase: > > > > @write_me = external global i32 > > @read_me = external global i32 > > > > ; Function Attrs: nounwind > > define i32 @xstg_...

Hi everyone I'm fairly new with LLVM and I've been searching around but couldn't find info on this subject. I started working on a target for a new cpu and I realizing my initial simple understanding of instruction itineraries may be completely off. I'm trying to model a CPU that has a latency of 2 cycles for multiplications fully pipelined (so it can start a new one after one cycle) First of all, is there a document that describes the instruction itinerary model in some detail ? For example looking at MBlaze targ...

Hello, Is there code in place for lowering the bitcode SSA into an optimized sequence for the itineraries? I have been curious whether or not such descriptions exist for the x86 family or whether there are techniques to make a clear determination of this information. Regards, Carter. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/...