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...and general store. Also, on the so-called "Book E" embedded PPC cores, the sync instruction is called msync (same opcode, different name). I'm not sure what the best way of doing a predicate-base asm name is. I'm just about done with a patch to add support for the FP2 (aka Double Hummer) v2f64 vector instruction set, but I figured that it would be good to make that a separate patch. Thanks in advance, Hal -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory -------------- next part -------------- A non-text attachment was scrubbed... Na...

...s called msync (same opcode, different name). I'm not sure what the > best way of doing a predicate-base asm name is. I am not sure how to do that. X86 has alternative syntaxes, but that is way overkill. > I'm just about done with a patch to add support for the FP2 (aka Double > Hummer) v2f64 vector instruction set, but I figured that it would be > good to make that a separate patch. Definitely. /jakob

Hello, I'm working on extending the current PowerPC backend to handle a vector instruction set for floating-point operations (IBM's double-hummer instruction set used on the BG/P supercomputers). In this instruction set, each of the existing floating-point registers becomes the first of two vector elements. I am having trouble optimizing the BUILD_VECTOR operation for the case where I am building a v2f64 vector out of two operands. I tried w...

...hare a store buffer. What > then? > I ask HW team about it but I have a question - has it any relationship with replacing MIPS SYNC with lightweight SYNCs (SYNC_WMB etc)? You use any barrier or do not use it and I just voice an intention to use a more efficient instruction instead of bold hummer (SYNC instruction). If you don't use any barrier here then it is a different issue. May be it has sense to return back to original issue? - Leonid

...hare a store buffer. What > then? > I ask HW team about it but I have a question - has it any relationship with replacing MIPS SYNC with lightweight SYNCs (SYNC_WMB etc)? You use any barrier or do not use it and I just voice an intention to use a more efficient instruction instead of bold hummer (SYNC instruction). If you don't use any barrier here then it is a different issue. May be it has sense to return back to original issue? - Leonid

...the same works fine when ruby is compiled in 32-bit. The platform is Sun OS 64-bit SPARC. But it is also reproduceable on Linux 64-bit Server. Here is the error: /home/venkatr/lib/ruby/1.8/yaml.rb:133: [BUG] Segmentation fault ruby 1.8.4 (2005-12-24) [sparc-solaris2.10] gem env output: [venkatr @hummer ~] gem env RubyGems Environment: - VERSION: 0.9.4 (0.9.4) - INSTALLATION DIRECTORY: /home/venkatr/v6ClientToolsInstallDir/gems - GEM PATH: - /home/venkatr/v6ClientToolsInstallDir/gems - /home/venkatr/v6ClientToolsInstallDir/lib/ruby/gems/1.8 - /home/venkatr/v6ClientToolsInstall...

(I try to answer on multiple mails in one) First of all, it seems like some generic notes should be given here: 1. Generic MIPS "SYNC" (aka "SYNC 0") instruction is a very heavy in some CPUs. On that CPUs it basically kills pipelines in each CPU, can do a special memory/IO bus transaction (similar to "fence") and hold a system until all R/W is completed. It is

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On Tue, 2012-05-01 at 19:58 -0500, Peter Bergner wrote: > On Tue, 2012-05-01 at 17:47 -0500, Hal Finkel wrote: > > By default it should build for > > whatever the current host is (no special flags required). To > > specifically build for something else, use: > > -ccc-host-triple powerpc64-unknown-linux-gnu > > or > > -ccc-host-triple