llvm dev - Dec 2017 - Schedules, latency and register liveness for complex instructions

Hi Martin,

 > The CPU that I am targeting is VLIW with no hardware interlocking 
(the next instruction does not wait for the previous to complete). This 
leads to fairly complex scheduling, but can be generally accommodated 
well in LLVM.


Thanks for sharing your usecase about instruction scheduling, I am 
learning Instruction Selector by reading ARM and AMDGPU target's source 
code, then I will try to port GlobalISel to AVR target, and implement 
Scheduling definition. So I argue that AMDGPU's scheduler might give you 
some hint? 
https://github.com/llvm-mirror/llvm/blob/master/lib/Target/AMDGPU/R600Schedule.td


-- 
Regards,
Leslie Zhai - https://reviews.llvm.org/p/xiangzhai/

Hi Leslie,

It is not the non-interlocked instruction scheduling that is the problem, it is
that each operand has its own schedule.  TableGen does not have a way (to the
best of my knowledge) of associating different schedules (register lifetimes)
with each of the operands of an instruction.  I already have the VLIW
instruction scheduling working very well, it is the nuances of how to also
handle these obscure and exotic instructions that do not fit the conventional
models that I am trying to solve.

Thanks,

	MartinO

-----Original Message-----
From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Leslie
Zhai via llvm-dev
Sent: 01 December 2017 17:35
To: llvm-dev at lists.llvm.org
Subject: Re: [llvm-dev] Schedules, latency and register liveness for complex
instructions

Hi Martin,

 > The CPU that I am targeting is VLIW with no hardware interlocking (the
next instruction does not wait for the previous to complete). This leads to
fairly complex scheduling, but can be generally accommodated well in LLVM.


Thanks for sharing your usecase about instruction scheduling, I am learning
Instruction Selector by reading ARM and AMDGPU target's source code, then I
will try to port GlobalISel to AVR target, and implement Scheduling definition.
So I argue that AMDGPU's scheduler might give you some hint?
https://github.com/llvm-mirror/llvm/blob/master/lib/Target/AMDGPU/R600Schedule.td


--
Regards,
Leslie Zhai - https://reviews.llvm.org/p/xiangzhai/



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Hi Martin,

Thanks for your kind response!

I just want to learn, then try to implement AVRSchedule.td, 
AVRScheduleAVR5.td for atmega328p device 
http://www.atmel.com/Images/Atmel-42735-8-bit-AVR-Microcontroller-ATmega328-328P_datasheet.pdf

Please share more how to make VLIW instruction scheduling work very well 
when each operand has its own scheduler. Or do you plan to refactory 
tablegen to support different schedules for each of the operands of an 
instruction? thanks a lot!


在 2017年12月02日 20:47, Martin J. O'Riordan 写道:
> Hi Leslie,
>
> It is not the non-interlocked instruction scheduling that is the problem,
it is that each operand has its own schedule.  TableGen does not have a way (to
the best of my knowledge) of associating different schedules (register
lifetimes) with each of the operands of an instruction.  I already have the VLIW
instruction scheduling working very well, it is the nuances of how to also
handle these obscure and exotic instructions that do not fit the conventional
models that I am trying to solve.
>
> Thanks,
>
> 	MartinO
>
> -----Original Message-----
> From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of
Leslie Zhai via llvm-dev
> Sent: 01 December 2017 17:35
> To: llvm-dev at lists.llvm.org
> Subject: Re: [llvm-dev] Schedules, latency and register liveness for
complex instructions
>
> Hi Martin,
>
>   > The CPU that I am targeting is VLIW with no hardware interlocking
(the next instruction does not wait for the previous to complete). This leads to
fairly complex scheduling, but can be generally accommodated well in LLVM.
>
>
> Thanks for sharing your usecase about instruction scheduling, I am learning
Instruction Selector by reading ARM and AMDGPU target's source code, then I
will try to port GlobalISel to AVR target, and implement Scheduling definition.
So I argue that AMDGPU's scheduler might give you some hint?
>
https://github.com/llvm-mirror/llvm/blob/master/lib/Target/AMDGPU/R600Schedule.td
>
>
> --
> Regards,
> Leslie Zhai - https://reviews.llvm.org/p/xiangzhai/
>
>
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
-- 
Regards,
Leslie Zhai - https://reviews.llvm.org/p/xiangzhai/