Displaying 2 results from an estimated 2 matches for "r600schedule".
2017 Dec 01
2
Schedules, latency and register liveness for complex instructions
...ning Instruction Selector by reading ARM and AMDGPU target's source
code, then I will try to port GlobalISel to AVR target, and implement
Scheduling definition. So I argue that AMDGPU's scheduler might give you
some hint?
https://github.com/llvm-mirror/llvm/blob/master/lib/Target/AMDGPU/R600Schedule.td
--
Regards,
Leslie Zhai - https://reviews.llvm.org/p/xiangzhai/
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
...MachineFunctionInfo.cpp
> llvm/trunk/lib/Target/AMDGPU/R600MachineFunctionInfo.h
> llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.cpp
> llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.h
> llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.td
> llvm/trunk/lib/Target/AMDGPU/R600Schedule.td
> llvm/trunk/lib/Target/AMDGPU/SIAssignInterpRegs.cpp
> llvm/trunk/lib/Target/AMDGPU/SICodeEmitter.cpp
> llvm/trunk/lib/Target/AMDGPU/SIGenRegisterInfo.pl
> llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
> llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h
>...