similar to: Schedules, latency and register liveness for complex instructions

Hi Leslie, On 20 December 2017 at 10:51, Leslie Zhai via llvm-dev <llvm-dev at lists.llvm.org> wrote: > Sorry, I am apprentice of lowRISC, and meet new bug when porting GlobalISel > to RISCV target > https://github.com/xiangzhai/llvm/commit/b3f91ea54d9fee0ef7e73a32c6b8456bbe252811 > > > In file included from >

Hi LLVM developers, llc -march=mips -debug-only=isel was able to work in Nov 8 2017 https://reviews.llvm.org/D39723 But it doesn't work now: $ clang --version LLVM China clang version 6.0.0 (git at github.com:llvm-mirror/clang.git 9b7b03045ee9b5622028537266aafeb9ea218ac1) (git at github.com:llvm-mirror/llvm.git 3a26601a88394c02603b8756527c55df9ab94d78) (based on LLVM 6.0.0svn) Target:

-debug-only only works on builds with assertions enabled. Your version string says optimized build and doesn’t mention assertions. On Thu, Dec 21, 2017 at 7:15 AM Leslie Zhai via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi LLVM developers, > > llc -march=mips -debug-only=isel was able to work in Nov 8 2017 > https://reviews.llvm.org/D39723 > > But it doesn't

Hi LLVM developers, As PR35281 mentioned: $ llvm-objcopy -O binary llvm-cortex-m7.elf llvm-cortex-m7.bin llvm-objcopy: 'llvm-cortex-m7.elf': The file was not recognized as a valid object file. if (ELFObjectFile<ELF64LE> *o = dyn_cast<ELFObjectFile<ELF64LE>>(&Binary)) https://github.com/llvm-mirror/llvm/blob/master/tools/llvm-objcopy/llvm-objcopy.cpp#L200

在 2017年04月26日 16:51, Simon Dardis 写道: > Hi Leslie, > > I've been seeing those failures as well (I own those buildbots). Like yourself, I'm a bit > uncertain as to why they're occurring. I'm currently investigating. I suspect it's a case > that the build directory has gone stale. Perhaps! and buildbots cover how many LLVM Backend targets? thanks! > >

Hi GCC and LLVM developers, I am learning Register Allocation algorithms and I am clear that: * Unlimited VirtReg (pseudo) -> limited or fixed or alias[1] PhysReg (hard) * Memory (20 - 100 cycles) is expensive than Register (1 cycle), but it has to spill code when PhysReg is unavailable * Folding spill code into instructions, handling register coallescing, splitting live ranges, doing

Hi LLVM developers, After Remove int_x86_sse2_psll_dq_bs and int_x86_sse2_psrl_dq_bs intrinsics. The builtins aren't used by clang. https://reviews.llvm.org/rL229069 there was no Intrinsic::x86_sse2_psrl_dq any more, then how to migrate: Function *F = Intrinsic::getDeclaration(TheModule, Intrinsic::x86_sse2_psrl_dq); Result = Builder.CreateCall(F,

Hi LLVM developers, Buildbot clang-cmake-mips False Positive? I have looked build failures: http://lab.llvm.org:8011/builders/clang-cmake-mips/builds/3277 http://lab.llvm.org:8011/builders/clang-cmake-mips/builds/3278 http://lab.llvm.org:8011/builders/clang-cmake-mips/builds/3279 http://lab.llvm.org:8011/builders/clang-cmake-mips/builds/3281

Hi LLVM and GCC developers, My sincere thanks will goto: * Duncan, the core developer of llvm-gcc and dragonegg http://llvm.org/devmtg/2009-10/Sands_LLVMGCCPlugin.pdf * David, the innovator and developer of GCC https://dmalcolm.fedorapeople.org/gcc/global-state/requirements.html and others who give me kind response for teaching me patiently and carefully about how to migrate GCC v4.8.x to

Reported https://bugs.llvm.org/show_bug.cgi?id=38911 Thanks, Leslie Zhai 在 2018年09月11日 16:55, Dimitry Andric 写道: > Hi Leslie, > > The problem really lies in the OpenJDK code, as it is attempting to > write to a const object. If this seems to work with certain compiler(s) > and optimization settings, it is just luck. :-) > > Here is a reduced example, which shows the

Hi Dimitry, Thanks for your kind response! Thanks for the commit message of Jung's patch, I found that the bug had been fixed in OpenJDK 12 by Zhengyu https://bugs.openjdk.java.net/browse/JDK-8205965 But only backported to 11. So Jung could backport it for OpenJDK 8, thanks a lot! But I argue that the root cause might be in the compiler side, why clang-3.9.1, gcc-6.4.1 couldn't

Hi LLVM developers, Thank Daniel Sanders, Aditya Nandakumar and Justin Bogner's Tutorial[1]: Head First into GlobalISel about how to port, and Aditya took BPF target as a simple instance: bool BPFCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,                                   const Value *Val, unsigned VReg) const {   assert(!Val == !VReg && "Return value

Hi all, Thanks for Aleksandar Beserminji great job: https://reviews.llvm.org/D50437 It is not easy to reproduce the LLVMBUG-38221[1] by building OpenJDK8, it needs some workaround https://raw.githubusercontent.com/xiangzhai/jdk8u-dev/master/Workaround-compile-with-llvm.patch LLVM toolchain[2] is just able to compile OpenJDK8 for mips64el now: http://hg.loongnix.org/ 1.

Hi LLVM developers, GCC[1] is able to use Loongson ISA[2] for instruction selection: $ cat hello.c #include <stdio.h> int main(int argc, char *argv[]) { printf("Hello World\n"); return 0; } $ gcc -O0 -S hello.c $ cat hello.s .file 1 "hello.c" .section .mdebug.abi64 .previous .nan legacy .gnu_attribute 4, 1 .abicalls

Hi Matthias, Thanks for your hint! It is just for learning and practicing for me, just like migrate DragonEgg http://lists.llvm.org/pipermail/llvm-dev/2017-September/117201.html the motivating is for learning from GCC and LLVM developers. 在 2017年12月19日 10:07, Matthias Braun 写道: > > >> On Dec 18, 2017, at 9:52 AM, Leslie Zhai via llvm-dev >> <llvm-dev at lists.llvm.org

Hi all, OpenJDK8 jdk8u-dev[1] is just able to work after compiled with LLVM 3.9.1 for X86: $ ./build/linux-x86_64-normal-server-slowdebug/images/j2sdk-image/bin/java -version openjdk version "1.8.0-internal-debug" OpenJDK Runtime Environment (build 1.8.0-internal-debug-xiangzhai_2018_09_09_21_08-b00) OpenJDK 64-Bit Server VM (build 25.71-b00-debug, mixed mode) $ strings

On Fri, Jan 5, 2018 at 12:51 AM Leslie Zhai via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi LLVM developers, > > Does it need to implement <Target>RetpolineThunksPass, > `getOpcodeForRetpoline`, `EmitLoweredRetpoline`, etc. for other Targets? > Or does it also need to implement `RetpolinePic` to inherit from > <Target> for LLD's Backends? Alex is my

- my old email address. The ISA_* classes might not be the best choice for this. There's an overall hierarchy and ordering to the ISA_* classes since they represent the generations of the MIPS ISA. If these extensions are available in Loongson chips based on MIPS32r1 and MIPS32r2 for example, it becomes difficult to describe with ISA_* classes without duplicating instruction definitions or

Hello Leslie, The errors coming from the gnu assembler are due to the file being assembled in Arm state, to get rid of the errors you'll either need to put a .thumb directive in the file, or pass -mthumb to the assembler via arm-linux-gnu-gcc -Wa,-mthumb (I think). I'm not able to explain what you are seeing in your print out as it doesn't quite match the map file. Looking at your

Hello Leslie, I think we are going to need to know a bit more about the ELF ABI for what looks like the ArcCompact before we can help you. LLD's calculation of P (the place to be relocated) is as it is in the generic ELF specification. The Rel.Offset corresponds to the ELF r_offset field. This is covered by: "For a relocatable file, the value is the byte offset from the beginning of the