Displaying 1 result from an estimated 1 matches for "avrscheduleavr5".
2017 Dec 01
2
Schedules, latency and register liveness for complex instructions
Hi Martin,
> The CPU that I am targeting is VLIW with no hardware interlocking
(the next instruction does not wait for the previous to complete). This
leads to fairly complex scheduling, but can be generally accommodated
well in LLVM.
Thanks for sharing your usecase about instruction scheduling, I am
learning Instruction Selector by reading ARM and AMDGPU target's source
code, then