llvm dev - Aug 2017 - Re-computing Live-in/Live-out Physical Registers for Basic Blocks Using LivePhysRegs

Thank you for your reply!

If liveness of APSR is not tracked, how does the code generator determine
whether instructions like cmp are dead code or not?
Is it true that, for every use of APSR (such as a conditional branch), the used
def (such as cmp, add, etc.) is always in the same basic block?
Is it true that APSR is never assumed to live across basic block boundaries?

Thank you!


Ming Zhang


>On Aug 2, 2017, at 9:07 AM, Matthias Braun via llvm-dev llvm-dev at
lists.llvm.org llvm-dev at lists.llvm.org>> wrote:
>Yes LivePhysRegs can do that for you. It has addLiveIns() and addLiveOuts()
functions to get the live-in or live-out set for a basic block (make the set is
empty when you call these functions).
>Yes APSR is marked as a reserved register by the ARM target, this means we
do not track liveness for it.
>- Matthias
>>On Aug 2, 2017, at 2:45 AM, 章明 via llvm-dev llvm-dev at lists.llvm.org
llvm-dev at lists.llvm.org>> wrote:
>>
>>Hi, LLVM developers! 
>>
>>
>>I am working on software control flow checking. I have to work at the
native assembly level, and rely on the code generator to provide various
information. I'm considering ARM Cortex-M3 as my target CPU.
>> 
>>
>>I would like to determine live-in and live-out PHYSICAL registers for
every machine basic block after all code generation passes, such as the ARM
Constant Island pass, and before code emission. Unfortunately, at this point,
information about live-in/live-out registers has been invalidated by the ARM
Constant Island pass. So I am considering re-computing it.
>>
>>
>>Class LivePhysRegs seems to be able to compute live-in/live-out
registers for a given machine basic block based on live-in registers of its
successors. It appears to me that, if I perform a depth-first traversal through
the control flow graph of a function, calling LivePhysRegs::computeLiveIns on
every machine basic block, live-in/live-out physical registers are computed for
every basic block. Is this true?
>> 
>>
>>Also, I would like to know whether APSR is dead or not on entry and exit
of every basic block. Is the register treated by LLVM specially or in the same
way as other general-purpose registers? >>>Thank you! 
>>>>Ming Zhang  >

It looks like LLVM uses the CPSR register to model compares and conditional
jumps. (I recommend writing some test programs and using -print-machineinstrs to
experiment yourself). APSR seems to be just a different name/alias for some of
the CPSR flags (including the NZCV used for conditional branching).

- Matthias
> On Aug 2, 2017, at 7:20 PM, 章明 via llvm-dev <llvm-dev at
lists.llvm.org> wrote:
> 
> Thank you for your reply!
> 
> If liveness of APSR is not tracked, how does the code generator determine
whether instructions like cmp are dead code or not?
> Is it true that, for every use of APSR (such as a conditional branch), the
used def (such as cmp, add, etc.) is always in the same basic block?
> Is it true that APSR is never assumed to live across basic block
boundaries?
> 
> Thank you!
> 
> 
> Ming Zhang
> 
> 
> 
>> On Aug 2, 2017, at 9:07 AM, Matthias Braun via llvm-dev llvm-dev at
lists.llvm.org llvm-dev at lists.llvm.org>> wrote:
> 
>> Yes LivePhysRegs can do that for you. It has addLiveIns() and
addLiveOuts() functions to get the live-in or live-out set for a basic block
(make the set is empty when you call these functions).
> 
>> Yes APSR is marked as a reserved register by the ARM target, this means
we do not track liveness for it.
> 
>> - Matthias
> 
>>> On Aug 2, 2017, at 2:45 AM, 章明 via llvm-dev llvm-dev at
lists.llvm.org llvm-dev at lists.llvm.org>> wrote:
> 
>>> 
>>> Hi, LLVM developers! 
>>> 
>>> 
>>> I am working on software control flow checking. I have to work at
the native assembly level, and rely on the code generator to provide various
information. I'm considering ARM Cortex-M3 as my target CPU.
>>> 
>>> 
>>> I would like to determine live-in and live-out PHYSICAL registers
for every machine basic block after all code generation passes, such as the ARM
Constant Island pass, and before code emission. Unfortunately, at this point,
information about live-in/live-out registers has been invalidated by the ARM
Constant Island pass. So I am considering re-computing it.
>>> 
>>> 
>>> Class LivePhysRegs seems to be able to compute live-in/live-out
registers for a given machine basic block based on live-in registers of its
successors. It appears to me that, if I perform a depth-first traversal through
the control flow graph of a function, calling LivePhysRegs::computeLiveIns on
every machine basic block, live-in/live-out physical registers are computed for
every basic block. Is this true?
>>> 
>>> 
>>> Also, I would like to know whether APSR is dead or not on entry and
exit of every basic block. Is the register treated by LLVM specially or in the
same way as other general-purpose registers? >>>Thank you! 
>>>>Ming Zhang  >
> 
> 
> 
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev

I have tried to build MC instructions using MCInstBuilder.
It does model APSR using CPSR. Adding ARM::APSR as a register operand would
trigger an assertion failure. When I use ARM::CPSR in place of ARM::APSR, the
instructions in the generated native assembly code use APSR as desired.

For my control flow checking instrumentation, I would like to minimize overhead
of additional instrumentation code inserted into the program code.
The instrumentation code may clobber APSR. I would like to use liveness
information of APSR to decide whether APSR needs to be saved or not for every
instrumentation code snippet.
If tracking liveness of APSR/CPSR is difficult, I may consider generating
instrumentation code that does not clobber it.

Thank you!

> -----Original Messages-----
> From: "Matthias Braun" <matze at braunis.de>
> Sent Time: 2017-08-08 00:44:10 (Tuesday)
> To: "章明" <editing at zju.edu.cn>
> Cc: llvm-dev at lists.llvm.org
> Subject: Re: [llvm-dev] Re-computing Live-in/Live-out Physical Registers
for Basic Blocks Using LivePhysRegs
> 
> It looks like LLVM uses the CPSR register to model compares and conditional
jumps. (I recommend writing some test programs and using -print-machineinstrs to
experiment yourself). APSR seems to be just a different name/alias for some of
the CPSR flags (including the NZCV used for conditional branching).
> 
> - Matthias
> 
> > On Aug 2, 2017, at 7:20 PM, 章明 via llvm-dev <llvm-dev at
lists.llvm.org> wrote:
> > 
> > Thank you for your reply!
> > 
> > If liveness of APSR is not tracked, how does the code generator
determine whether instructions like cmp are dead code or not?
> > Is it true that, for every use of APSR (such as a conditional branch),
the used def (such as cmp, add, etc.) is always in the same basic block?
> > Is it true that APSR is never assumed to live across basic block
boundaries?
> > 
> > Thank you!
> > 
> > 
> > Ming Zhang
> > 
> > 
> > 
> >> On Aug 2, 2017, at 9:07 AM, Matthias Braun via llvm-dev llvm-dev
at lists.llvm.org llvm-dev at lists.llvm.org>> wrote:
> > 
> >> Yes LivePhysRegs can do that for you. It has addLiveIns() and
addLiveOuts() functions to get the live-in or live-out set for a basic block
(make the set is empty when you call these functions).
> > 
> >> Yes APSR is marked as a reserved register by the ARM target, this
means we do not track liveness for it.
> > 
> >> - Matthias
> > 
> >>> On Aug 2, 2017, at 2:45 AM, 章明 via llvm-dev llvm-dev at
lists.llvm.org llvm-dev at lists.llvm.org>> wrote:
> > 
> >>> 
> >>> Hi, LLVM developers! 
> >>> 
> >>> 
> >>> I am working on software control flow checking. I have to work
at the native assembly level, and rely on the code generator to provide various
information. I'm considering ARM Cortex-M3 as my target CPU.
> >>> 
> >>> 
> >>> I would like to determine live-in and live-out PHYSICAL
registers for every machine basic block after all code generation passes, such
as the ARM Constant Island pass, and before code emission. Unfortunately, at
this point, information about live-in/live-out registers has been invalidated by
the ARM Constant Island pass. So I am considering re-computing it.
> >>> 
> >>> 
> >>> Class LivePhysRegs seems to be able to compute
live-in/live-out registers for a given machine basic block based on live-in
registers of its successors. It appears to me that, if I perform a depth-first
traversal through the control flow graph of a function, calling
LivePhysRegs::computeLiveIns on every machine basic block, live-in/live-out
physical registers are computed for every basic block. Is this true?
> >>> 
> >>> 
> >>> Also, I would like to know whether APSR is dead or not on
entry and exit of every basic block. Is the register treated by LLVM specially
or in the same way as other general-purpose registers? >>>Thank you! 
>>>>Ming Zhang  >
> > 
> > 
> > 
> > _______________________________________________
> > LLVM Developers mailing list
> > llvm-dev at lists.llvm.org
> > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev