search for: apsr

Thank you for your reply! If liveness of APSR is not tracked, how does the code generator determine whether instructions like cmp are dead code or not? Is it true that, for every use of APSR (such as a conditional branch), the used def (such as cmp, add, etc.) is always in the same basic block? Is it true that APSR is never assumed to live acr...

.../richards/llvm/src/test/MC/ARM/basic -thumb2-instructions.s | /home/richards/llvm/build/Debug+Asserts/bin/FileCheck /home/richards/llvm/src/test/MC/ARM/basic-thumb2-instructions.s -- Exit Code: 1 Command Output (stderr): -- <stdin>:1356:9: error: instruction requires: armv7m mrs r8, apsr ^ <stdin>:1357:9: error: instruction requires: armv7m mrs r8, cpsr ^ <stdin>:1358:9: error: instruction requires: armv7m mrs r8, spsr ^ and the second was the same for basic-arm-instructions.s. The problem seems to be that the MSRMask parser i...

...rget>GenRegisterInfo.inc. These numbers don't have any meaning other than to represent a particular register. The 0x01 would be the encoding used in generating the binary. The D0 has id 14 on ARM because there are 13 other registers preceding it: namespace ARM { enum { NoRegister, APSR = 1, APSR_NZCV = 2, CPSR = 3, FPEXC = 4, FPINST = 5, FPSCR = 6, FPSCR_NZCV = 7, FPSID = 8, ITSTATE = 9, LR = 10, PC = 11, SP = 12, SPSR = 13, D0 = 14, ... -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Lin...

> /tmp/foo.s:1:2: error: instruction requires: distinct-ops > sllk %r2,%r3,1 > ^ That seems like it would be a good improvement for all targets. > ARM seems to rely on the current MatchOperandParserImpl() behaviour, > so I'm not going to suggest changing it unconditionally. Presumably you switched it and looked at what fell over; do you remember what kind

Dear all, in my TestRegisterInfo.td file, I defined a register like this: class TestReg<bits<6> enc, string name> : Register<name> { let HWEncoding{5-0} = enc; let Namespace = "TEST"; } def D0 : TestReg<0x01, "d0">, DwarfRegNum<[1]>; but when I compile, the result I have in TestGenAsmMatcher.inc is this: case 'd': // 7

...ic > -thumb2-instructions.s | /home/richards/llvm/build/Debug+Asserts/bin/FileCheck /home/richards/llvm/src/test/MC/ARM/basic-thumb2-instructions.s > -- > Exit Code: 1 > Command Output (stderr): > -- > <stdin>:1356:9: error: instruction requires: armv7m > mrs r8, apsr > ^ > <stdin>:1357:9: error: instruction requires: armv7m > mrs r8, cpsr > ^ > <stdin>:1358:9: error: instruction requires: armv7m > mrs r8, spsr > ^ > > and the second was the same for basic-arm-instructions.s. The probl...

I'm trying to add some instructions that are only available on certain processors. These instructions use context-dependent parsers. Everything works fine for the valid cases, but if you try to use an instruction on processors that don't support it, the asm parser says: /tmp/foo.s:1:2: error: invalid operands for instruction sllk %r2,%r3,1 ^ rather than:

...ore-Exclusive having returned a fail result and the retry of the Load-Exclusive: – There are no stores to any location within the same Exclusives reservation granule that the StoreExclusive is accessing. – There are no direct or indirect register writes, other than changes to the flag fields in APSR or FPSCR, caused by data processing or comparison instructions. – There are no direct or indirect cache maintenance instructions, SVC instructions, or exception returns """ Of course it also states that the upper limit for the Exclusives Reservation Granule is 2048 bytes, but the...

# RFC: Atomic LL/SC loops in LLVM revisited ## Summary This proposal gives a brief overview of the challenges of lowering to LL/SC loops and details the approach I am taking for RISC-V. Beyond getting feedback on that work, my intention is to find consensus on moving other backends towards a similar approach and sharing common code where feasible. Scroll down to 'Questions' for a summary