search for: addliveouts

Displaying 6 results from an estimated 6 matches for "addliveouts".

2013 Feb 02
0
[LLVMdev] Moving return value registers from MRI to return instructions
MachineRegisterInfo is maintaining a list of live-out registers for the MachineFunction. It contains the return value registers, and is typically created by XXXISelLowering::LowerReturn(). Various passes after instruction selection need to look at this list to determine which physical registers are live in return blocks. Eventually, the register allocators copy these live-out registers onto the
2006 May 31
0
[LLVMdev] [RFC, ARM] expanding RET to CopyToReg;BRIND
On Wed, 31 May 2006, [UTF-8] Rafael Esp?ndola wrote: >> We don't want the copy and shift to wander apart from each other (e.g. we >> don't want another shift to get scheduled in between them), so we flag >> them together. In practice, these copies usually get coallesced away. > In the second case shl explicitly uses CL. Shouldn't the register > allocator be
2006 May 31
1
[LLVMdev] [RFC, ARM] expanding RET to CopyToReg;BRIND
On 5/31/06, Chris Lattner <sabre at nondot.org> wrote: > On Wed, 31 May 2006, [UTF-8] Rafael Esp?ndola wrote: > >> We don't want the copy and shift to wander apart from each other (e.g. we > >> don't want another shift to get scheduled in between them), so we flag > >> them together. In practice, these copies usually get coallesced away. > > In
2017 Aug 03
2
Re-computing Live-in/Live-out Physical Registers for Basic Blocks Using LivePhysRegs
...it true that APSR is never assumed to live across basic block boundaries? Thank you! Ming Zhang >On Aug 2, 2017, at 9:07 AM, Matthias Braun via llvm-dev llvm-dev at lists.llvm.org llvm-dev at lists.llvm.org>> wrote: >Yes LivePhysRegs can do that for you. It has addLiveIns() and addLiveOuts() functions to get the live-in or live-out set for a basic block (make the set is empty when you call these functions). >Yes APSR is marked as a reserved register by the ARM target, this means we do not track liveness for it. >- Matthias >>On Aug 2, 2017, at 2:45 AM, 章明 via llvm-dev...
2006 May 31
2
[LLVMdev] [RFC, ARM] expanding RET to CopyToReg;BRIND
> > Why it is named RETFLAG? > > Historical reason. Originally we didn't have nodes that could > *optionally* have an input flag. A better design, e.g. on PPC would be to > have a PPCISD::RET node, which takes an optional input flag, and always > lower RET to it. I See. I will try to always lower to "(mov)*;bx lr" on ARM. > Flag in the SelectionDAG stuff is
2012 Dec 03
1
[LLVMdev] operator overloading fails while debugging with gdb for i386
On 3 December 2012 10:42, Mayur Pandey <mayurthebond at gmail.com> wrote: > So this seems to be the cause of the problem. I guess you're mixing two different problems. First, is the possible lack of conformance with the ABI you state, which I can't comment since I don't know that ABI very well. Second, is the fact that clang is not printing correct debug information (or is