Displaying 20 results from an estimated 3000 matches similar to: "Re-computing Live-in/Live-out Physical Registers for Basic Blocks Using LivePhysRegs"
2013 Jul 17
2
[LLVMdev] Help with subtarget features and context-dependent asm parsers
Tim Northover <t.p.northover at gmail.com> writes:
>> /tmp/foo.s:1:2: error: instruction requires: distinct-ops
>> sllk %r2,%r3,1
>> ^
>
> That seems like it would be a good improvement for all targets.
Thanks, sounds like it might be more acceptable than I thought :-)
>> ARM seems to rely on the current MatchOperandParserImpl() behaviour,
2014 Oct 14
2
[LLVMdev] Thoughts on maintaining liveness information for stackmaps
I think what's happening is BranchFolder::MaintainLiveIns is using a
forward analysis on top of these missing kill flags, and updating the
BB-live-ins/live-outs with an incorrect set of registers. Then when the
stackmaps liveness analysis happens, it's not doing anything wrong, but it
starts with the wrong set of live registers and will propagate those to the
point of the
2015 Sep 17
2
Register Number
On 9/17/2015 7:04 AM, Sky Flyer via llvm-dev wrote:
> It seems like d0 is always 14!
> I check it with ARMGenAsmMatcher.inc it was the same!
> How is it possible? because it should give the same register value that
> matches the underlying platform not any autogenerated value!?
The returned number is the register id as defined in
<YourTarget>GenRegisterInfo.inc. These numbers
2016 Nov 21
2
Conditional jump or move depends on uninitialised value(s)
I spent some time digging into a Valgrind report of uninitialized values
in LLVM r287520 built using itself. (One of quite a few such reports
that comes up during a "make check".)
I could use another set of eyes on the issue if someone has time.
This command gives me an error:
valgrind -q ./bin/llc <
/home/regehr/llvm/test/CodeGen/Hexagon/hwloop-dbg.ll -march=hexagon
2010 Apr 14
0
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
On Apr 14, 2010, at 1:55 PMPDT, Villmow, Micah wrote:
> I’ve recently sync’d to a newer version of LLVM(Apple branch 2326 from Apple branch 2323.8) that changed the interface to addCommonCodeGenPasses which caused the default implementation to be executed instead of my overriding implementation. This default implementation has DeadMachineInstructionElim pass enabled, which is causing havoc
2010 Apr 14
2
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
I've recently sync'd to a newer version of LLVM(Apple branch 2326 from Apple branch 2323.8) that changed the interface to addCommonCodeGenPasses which caused the default implementation to be executed instead of my overriding implementation. This default implementation has DeadMachineInstructionElim pass enabled, which is causing havoc with my backend. Before entering this pass, everything
2016 Nov 22
2
Conditional jump or move depends on uninitialised value(s)
Just want to emphasize that on x86-64 and using Valgrind:
LLVM compiled with LLVM gets 360 unexpected test fails
LLVM compiled with GCC gets 22 unexpected test fails
Of course I don't know how many of these are caused by this bitfield
speculation issue.
John
On 11/21/2016 10:48 PM, regehr via llvm-dev wrote:
> Alright, here's what seems to be happening...
>
> The testcase
2010 Apr 14
2
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
Dale,
Yeah that is correct, so that isn't the problem, not sure why I was thinking it is. The !MRI->use_no_dbg_empty(Reg) seems to be correct and the problem is LivePhysRegs[Reg] always returning false. I've looked into this more and there is a part where I'm working with physical registers.
If there is a function call, there is a copy from virtual register space to the functions
2018 Feb 13
2
Undef physical registers?
Hi,
I'm a bit unsure of the semantics of undef physical registers. The explanations I've seen in the code and in the langref seems to
pertain more to constant values and virtual registers.
What I really want to achieve is a push-pop of a register to have a temporary to work with, without having to check if this
register is defined or not. However, whenever the reg is not defined before
2014 Oct 14
2
[LLVMdev] Thoughts on maintaining liveness information for stackmaps
Hi all, I've run into a couple bugs recently that affected stackmap
liveness analysis in various ways:
http://llvm.org/bugs/show_bug.cgi?id=19224 - function arguments stay live
unnecessarily
http://llvm.org/bugs/show_bug.cgi?id=21265 - eflags can end up as a live out
http://llvm.org/bugs/show_bug.cgi?id=21266 - %rip can end up as a live out
The first two have nothing to do with stackmaps
2017 Nov 11
2
Update control flow graph when splitting a machine basic block?
> The right way to update the CFG very much depends on how you're
> transforming it.
I would like to export the CFG for control flow checking.
Theoretically, it should be possible for a compiler to know every target of every control flow instruction, except for computed targets that are not known at compile-time.
When a machine basic block is split between two branches, as shown below:
2013 Jul 17
0
[LLVMdev] Help with subtarget features and context-dependent asm parsers
> /tmp/foo.s:1:2: error: instruction requires: distinct-ops
> sllk %r2,%r3,1
> ^
That seems like it would be a good improvement for all targets.
> ARM seems to rely on the current MatchOperandParserImpl() behaviour,
> so I'm not going to suggest changing it unconditionally.
Presumably you switched it and looked at what fell over; do you
remember what kind
2015 Sep 17
2
Register Number
Dear all,
in my TestRegisterInfo.td file, I defined a register like this:
class TestReg<bits<6> enc, string name> : Register<name> {
let HWEncoding{5-0} = enc;
let Namespace = "TEST";
}
def D0 : TestReg<0x01, "d0">, DwarfRegNum<[1]>;
but when I compile, the result I have in TestGenAsmMatcher.inc is this:
case 'd': // 7
2011 Sep 07
1
[LLVMdev] ARM CPSR liveness
All,
ARM LLVM afficianados: I'm trying to understand how LiveVariables computes
liveness for CPSR. In particular,
I would like to tell whether a particular instruction is a use/kill/def for
doing some within block liveness checking I need.
Thanks in advance,
David
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2013 Jul 17
2
[LLVMdev] Help with subtarget features and context-dependent asm parsers
I'm trying to add some instructions that are only available on certain
processors. These instructions use context-dependent parsers. Everything
works fine for the valid cases, but if you try to use an instruction on
processors that don't support it, the asm parser says:
/tmp/foo.s:1:2: error: invalid operands for instruction
sllk %r2,%r3,1
^
rather than:
2017 Nov 11
2
Update control flow graph when splitting a machine basic block?
Thank you for your reply!
> Every MachineBasicBlock has a list of successors; you can access it with
> the successors() accessor. That's what you should be using for any CFG
> analysis.
I am aware of these methods of class MachineBasicBlock, which allows one to access a MachineBasicBlock's successors and predecessors in the CFG.
But the CFG itself may no longer be valid if a
2017 Jul 17
2
Is clang+llvm deterministisc?
I searched source code of LLVM/Clang 4.0.0 for 'random_seed' with grep. It seems the -frandom-seed option is not supported.
The -rng-seed option appears to be defined in ./lib/Support/RandomNumberGenerator.cpp, which is source code for class RandomNumberGenerator. The constructor of class RandomNumberGenerator is private and is only called by Module::createRNG (defined in
2012 Feb 04
4
[LLVMdev] ARMLoadStoreOptimizer bug
Evan & llvmdev,
I'm seeing a case where ARM Load/Store optimizer is breaking code. I have
not had any luck trying to come up with a minimal example; it is breaking
in our stage 2 LLVM build.
But here's what I'm seeing in the debug output:
# Before ARMLoadStoreOptimizer:
BB#21: derived from LLVM BB %cond.end
Live Ins: %LR %R0 %R1 %R7 %R10 %R11
Predecessors according to
2013 Jul 17
0
[LLVMdev] Help with subtarget features and context-dependent asm parsers
On Jul 17, 2013, at 10:26 AM, Richard Sandiford <rsandifo at linux.vnet.ibm.com> wrote:
> Tim Northover <t.p.northover at gmail.com> writes:
>>> /tmp/foo.s:1:2: error: instruction requires: distinct-ops
>>> sllk %r2,%r3,1
>>> ^
>>
>> That seems like it would be a good improvement for all targets.
>
> Thanks, sounds
2010 Apr 29
0
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
Ping. Anyone have any idea on how to fix this?
Thanks,
Micah
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah
Sent: Wednesday, April 14, 2010 2:28 PM
To: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
Dale,
Yeah that is correct, so that isn't the problem, not sure