search for: addliveout

...s in functions calling builtin_eh_return(). The EH_RETURN pseudo-instruction has different return-value registers than normal return instructions. See PR14750 for the details. To fix this, I am going to remove the live-out lists from MachineRegisterInfo. These functions are going to be removed: - addLiveOut() - liveout_begin() - liveout_end() - isLiveOut() Instead of calling MRI.addLiveOut(), targets should add return value registers as implicit operands on return instructions. This is already how argument registers are passed to call instructions, making calls and returns work the same way. I'l...

...PPC::R3) You can play games like that, but I wouldn't suggest it. It's better to just force the copy to be inserted in the right place. When the register allocator runs, it does know about register lifetimes and other constraints, and knows that R3/R4 are live out (as indicated by MF.addLiveOut(...) ). -Chris -- http://nondot.org/sabre/ http://llvm.org/

...n play games like that, but I wouldn't suggest it. It's better to > just force the copy to be inserted in the right place. When the register > allocator runs, it does know about register lifetimes and other > constraints, and knows that R3/R4 are live out (as indicated by > MF.addLiveOut(...) ). I am going to use the Flag by now :-) I was just thinking that the imposed restriction is stronger then necessary. For example, it might be valid to reorder R3 = ... R4 = ... blr into R4 = .. R3 = ... blr > -Chris Thanks once more, Rafael

...it true that APSR is never assumed to live across basic block boundaries? Thank you! Ming Zhang >On Aug 2, 2017, at 9:07 AM, Matthias Braun via llvm-dev llvm-dev at lists.llvm.org llvm-dev at lists.llvm.org>> wrote: >Yes LivePhysRegs can do that for you. It has addLiveIns() and addLiveOuts() functions to get the live-in or live-out set for a basic block (make the set is empty when you call these functions). >Yes APSR is marked as a reserved register by the ARM target, this means we do not track liveness for it. >- Matthias >>On Aug 2, 2017, at 2:45 AM, 章明 via llvm-dev...

> > Why it is named RETFLAG? > > Historical reason. Originally we didn't have nodes that could > *optionally* have an input flag. A better design, e.g. on PPC would be to > have a PPCISD::RET node, which takes an optional input flag, and always > lower RET to it. I See. I will try to always lower to "(mov)*;bx lr" on ARM. > Flag in the SelectionDAG stuff is

On 3 December 2012 10:42, Mayur Pandey <mayurthebond at gmail.com> wrote: > So this seems to be the cause of the problem. I guess you're mixing two different problems. First, is the possible lack of conformance with the ABI you state, which I can't comment since I don't know that ABI very well. Second, is the fact that clang is not printing correct debug information (or is