X86: expose HLE/RTM features to dom0
Intel recently release 2 new features, HLE and TRM.
Refer to http://software.intel.com/file/41417.
This patch expose them to dom0.
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
diff -r 92e03310878f xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c Wed Feb 08 21:05:52 2012 +0800
+++ b/xen/arch/x86/traps.c Mon Feb 27 02:23:42 2012 +0800
@@ -857,9 +857,11 @@
case 0x00000007:
if ( regs->ecx == 0 )
b &= (cpufeat_mask(X86_FEATURE_BMI1) |
+ cpufeat_mask(X86_FEATURE_HLE) |
cpufeat_mask(X86_FEATURE_AVX2) |
cpufeat_mask(X86_FEATURE_BMI2) |
cpufeat_mask(X86_FEATURE_ERMS) |
+ cpufeat_mask(X86_FEATURE_RTM) |
cpufeat_mask(X86_FEATURE_FSGSBASE));
else
b = 0;
diff -r 92e03310878f xen/include/asm-x86/cpufeature.h
--- a/xen/include/asm-x86/cpufeature.h Wed Feb 08 21:05:52 2012 +0800
+++ b/xen/include/asm-x86/cpufeature.h Mon Feb 27 02:23:42 2012 +0800
@@ -149,11 +149,13 @@
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 7 */
#define X86_FEATURE_FSGSBASE (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
#define X86_FEATURE_BMI1 (7*32+ 3) /* 1st bit manipulation extensions */
+#define X86_FEATURE_HLE (7*32+ 4) /* Hardware Lock Elision */
#define X86_FEATURE_AVX2 (7*32+ 5) /* AVX2 instructions */
#define X86_FEATURE_SMEP (7*32+ 7) /* Supervisor Mode Execution Protection */
#define X86_FEATURE_BMI2 (7*32+ 8) /* 2nd bit manipulation extensions */
#define X86_FEATURE_ERMS (7*32+ 9) /* Enhanced REP MOVSB/STOSB */
#define X86_FEATURE_INVPCID (7*32+10) /* Invalidate Process Context ID */
+#define X86_FEATURE_RTM (7*32+11) /* Restricted Transactional Memory */
#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
#define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability)
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
http://lists.xen.org/xen-devel
>>> On 28.02.12 at 06:09, "Liu, Jinsong" <jinsong.liu@intel.com> wrote: > X86: expose HLE/RTM features to dom0 > > Intel recently release 2 new features, HLE and TRM. > Refer to http://software.intel.com/file/41417. > This patch expose them to dom0.While I committed this as obviously correct and desirable, I wonder what plans you have with this feature wrt - permitting use for HVM guests - permitting use in pv DomU - actual use in the hypervisor itself - use in Linux (afaict impossible at least for HLE with ticket locks, yet HLE is certainly the more desirable first step) Thanks, Jan
>>> On 28.02.12 at 09:12, "Jan Beulich" <JBeulich@suse.com> wrote: >>>> On 28.02.12 at 06:09, "Liu, Jinsong" <jinsong.liu@intel.com> wrote: >> X86: expose HLE/RTM features to dom0 >> >> Intel recently release 2 new features, HLE and TRM. >> Refer to http://software.intel.com/file/41417. >> This patch expose them to dom0. > > While I committed this as obviously correct and desirable, I wonder > what plans you have with this feature wrt > - permitting use for HVM guests > - permitting use in pv DomUJust saw that you already sent a patch to that effect (albeit to IanC instead of IanJ). Jan> - actual use in the hypervisor itself > - use in Linux (afaict impossible at least for HLE with ticket locks, yet > HLE is certainly the more desirable first step) > > Thanks, Jan > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xen.org > http://lists.xen.org/xen-devel
> - actual use in the hypervisor itself > - use in Linux (afaict impossible at least for HLE with ticket locks, yetJan, We are working on the first one. I know someone is working on the kernel side, but I don''t know any details. But HLE should be useful for a lock(not fine grained) for protecting an in-memory data structure that are actually grasped by different lock holders to access different data fields(which are non-relevant to each other). It might not be the cases for Xen hypervisor. We need profile and see. Shan Haitao> -----Original Message----- > From: xen-devel-bounces@lists.xen.org [mailto:xen-devel- > bounces@lists.xen.org] On Behalf Of Jan Beulich > Sent: Tuesday, February 28, 2012 4:12 PM > To: Liu, Jinsong > Cc: xen-devel@lists.xensource.com; keir.xen@gmail.com; Ian Campbell > Subject: Re: [Xen-devel] [Patch] X86: expose HLE/RTM features to dom0 > > >>> On 28.02.12 at 06:09, "Liu, Jinsong" <jinsong.liu@intel.com> wrote: > > X86: expose HLE/RTM features to dom0 > > > > Intel recently release 2 new features, HLE and TRM. > > Refer to http://software.intel.com/file/41417. > > This patch expose them to dom0. > > While I committed this as obviously correct and desirable, I wonder what > plans you have with this feature wrt > - permitting use for HVM guests > - permitting use in pv DomU > - actual use in the hypervisor itself > - use in Linux (afaict impossible at least for HLE with ticket locks, yet > HLE is certainly the more desirable first step) > > Thanks, Jan > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xen.org > http://lists.xen.org/xen-devel_______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel