Displaying 2 results from an estimated 2 matches for "x86_feature_bmi1".
2012 Sep 20
0
[PATCH 3/3] Expose tsc adjust to hvm guest
...800
+++ b/tools/libxc/xc_cpufeature.h Thu Sep 20 21:50:55 2012 +0800
@@ -128,6 +128,7 @@
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
#define X86_FEATURE_FSGSBASE 0 /* {RD,WR}{FS,GS}BASE instructions */
+#define X86_FEATURE_TSC_ADJUST 1 /* Tsc thread offset */
#define X86_FEATURE_BMI1 3 /* 1st group bit manipulation extensions */
#define X86_FEATURE_HLE 4 /* Hardware Lock Elision */
#define X86_FEATURE_AVX2 5 /* AVX2 instructions */
diff -r a6d12a1bc758 tools/libxc/xc_cpuid_x86.c
--- a/tools/libxc/xc_cpuid_x86.c Thu Sep 20 00:03:25 2012 +0800
+++ b/too...
2012 Feb 28
3
[Patch] X86: expose HLE/RTM features to dom0
...t;jinsong.liu@intel.com>
diff -r 92e03310878f xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c Wed Feb 08 21:05:52 2012 +0800
+++ b/xen/arch/x86/traps.c Mon Feb 27 02:23:42 2012 +0800
@@ -857,9 +857,11 @@
case 0x00000007:
if ( regs->ecx == 0 )
b &= (cpufeat_mask(X86_FEATURE_BMI1) |
+ cpufeat_mask(X86_FEATURE_HLE) |
cpufeat_mask(X86_FEATURE_AVX2) |
cpufeat_mask(X86_FEATURE_BMI2) |
cpufeat_mask(X86_FEATURE_ERMS) |
+ cpufeat_mask(X86_FEATURE_RTM) |
cpufeat_mask(X86_...