Displaying 7 results from an estimated 7 matches for "x86_feature_erm".
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x86_feature_erms
2017 Oct 04
0
[PATCH 09/13] x86/asm: Convert ALTERNATIVE*() assembler macros to preprocessor macros
...h/x86/lib/memcpy_64.S
index 9a53a06e5a3e..7ada0513864b 100644
--- a/arch/x86/lib/memcpy_64.S
+++ b/arch/x86/lib/memcpy_64.S
@@ -28,8 +28,8 @@
*/
ENTRY(__memcpy)
ENTRY(memcpy)
- ALTERNATIVE_2 "jmp memcpy_orig", "", X86_FEATURE_REP_GOOD, \
- "jmp memcpy_erms", X86_FEATURE_ERMS
+ ALTERNATIVE_2(jmp memcpy_orig, , X86_FEATURE_REP_GOOD,
+ jmp memcpy_erms, X86_FEATURE_ERMS)
movq %rdi, %rax
movq %rdx, %rcx
diff --git a/arch/x86/lib/memmove_64.S b/arch/x86/lib/memmove_64.S
index 15de86cd15b0..ca6c39effa2f 100644
--- a/arch/x86/lib/memmove_64.S
+++ b/arch/x86/lib/m...
2012 Feb 28
3
[Patch] X86: expose HLE/RTM features to dom0
...case 0x00000007:
if ( regs->ecx == 0 )
b &= (cpufeat_mask(X86_FEATURE_BMI1) |
+ cpufeat_mask(X86_FEATURE_HLE) |
cpufeat_mask(X86_FEATURE_AVX2) |
cpufeat_mask(X86_FEATURE_BMI2) |
cpufeat_mask(X86_FEATURE_ERMS) |
+ cpufeat_mask(X86_FEATURE_RTM) |
cpufeat_mask(X86_FEATURE_FSGSBASE));
else
b = 0;
diff -r 92e03310878f xen/include/asm-x86/cpufeature.h
--- a/xen/include/asm-x86/cpufeature.h Wed Feb 08 21:05:52 2012 +0800
+++ b/xen/include/asm-x86/cpu...
2011 Nov 24
0
[PATCH 4/6] X86: Disable PCID/INVPCID for pv
...19 /* Streaming SIMD Extensions 4.1 */
#define X86_FEATURE_SSE4_2 20 /* Streaming SIMD Extensions 4.2 */
@@ -132,5 +133,6 @@
#define X86_FEATURE_SMEP 7 /* Supervisor Mode Execution Protection */
#define X86_FEATURE_BMI2 8 /* 2nd group bit manipulation extensions */
#define X86_FEATURE_ERMS 9 /* Enhanced REP MOVSB/STOSB */
+#define X86_FEATURE_INVPCID 10 /* Invalidate Process Context ID */
#endif /* __LIBXC_CPUFEATURE_H */
diff -r 0b15aa9541dc tools/libxc/xc_cpuid_x86.c
--- a/tools/libxc/xc_cpuid_x86.c Thu Nov 17 18:41:59 2011 +0800
+++ b/tools/libxc/xc_cpuid_x86.c Thu...
2011 Nov 24
0
[PATCH 5/6] X86: Prepare PCID/INVPCID for hvm
...bitmaskof(X86_FEATURE_SSE4_2) |
bitmaskof(X86_FEATURE_MOVBE) |
@@ -363,6 +364,7 @@ static void xc_cpuid_hvm_policy(
bitmaskof(X86_FEATURE_SMEP) |
bitmaskof(X86_FEATURE_BMI2) |
bitmaskof(X86_FEATURE_ERMS) |
+ bitmaskof(X86_FEATURE_INVPCID) |
bitmaskof(X86_FEATURE_FSGSBASE));
} else
regs[1] = 0;
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2017 Oct 04
31
[PATCH 00/13] x86/paravirt: Make pv ops code generation more closely match reality
This changes the pv ops code generation to more closely match reality.
For example, instead of:
callq *0xffffffff81e3a400 (pv_irq_ops.save_fl)
vmlinux will now show:
pushfq
pop %rax
nop
nop
nop
nop
nop
which is what the runtime version of the code will show in most cases.
This idea was suggested by Andy Lutomirski.
The benefits are:
- For the most common runtime cases
2017 Oct 04
31
[PATCH 00/13] x86/paravirt: Make pv ops code generation more closely match reality
This changes the pv ops code generation to more closely match reality.
For example, instead of:
callq *0xffffffff81e3a400 (pv_irq_ops.save_fl)
vmlinux will now show:
pushfq
pop %rax
nop
nop
nop
nop
nop
which is what the runtime version of the code will show in most cases.
This idea was suggested by Andy Lutomirski.
The benefits are:
- For the most common runtime cases
2013 Jun 04
12
[PATCH 0/4] XSA-52..54 follow-up
The first patch really isn''t as much of a follow-up than what triggered
the security issues to be noticed in the first place.
1: x86: preserve FPU selectors for 32-bit guest code
2: x86: fix XCR0 handling
3: x86/xsave: adjust state management
4: x86/fxsave: bring in line with recent xsave adjustments
The first two I would see as candidates for 4.3 (as well as
subsequent backporting,