Expose tsc adjust to hvm guest
Intel latest SDM (17.13.3) release a new MSR
CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported.
This patch expose it to hvm guest.
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
diff -r a6d12a1bc758 tools/libxc/xc_cpufeature.h
--- a/tools/libxc/xc_cpufeature.h Thu Sep 20 00:03:25 2012 +0800
+++ b/tools/libxc/xc_cpufeature.h Thu Sep 20 21:50:55 2012 +0800
@@ -128,6 +128,7 @@
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
#define X86_FEATURE_FSGSBASE 0 /* {RD,WR}{FS,GS}BASE instructions */
+#define X86_FEATURE_TSC_ADJUST 1 /* Tsc thread offset */
#define X86_FEATURE_BMI1 3 /* 1st group bit manipulation extensions */
#define X86_FEATURE_HLE 4 /* Hardware Lock Elision */
#define X86_FEATURE_AVX2 5 /* AVX2 instructions */
diff -r a6d12a1bc758 tools/libxc/xc_cpuid_x86.c
--- a/tools/libxc/xc_cpuid_x86.c Thu Sep 20 00:03:25 2012 +0800
+++ b/tools/libxc/xc_cpuid_x86.c Thu Sep 20 21:50:55 2012 +0800
@@ -362,7 +362,8 @@
case 0x00000007: /* Intel-defined CPU features */
if ( input[1] == 0 ) {
- regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
+ regs[1] &= (bitmaskof(X86_FEATURE_TSC_ADJUST) |
+ bitmaskof(X86_FEATURE_BMI1) |
bitmaskof(X86_FEATURE_HLE) |
bitmaskof(X86_FEATURE_AVX2) |
bitmaskof(X86_FEATURE_SMEP) |
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