similar to: [Patch] X86: expose HLE/RTM features to dom0

Expose tsc adjust to hvm guest Intel latest SDM (17.13.3) release a new MSR CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported. This patch expose it to hvm guest. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> diff -r a6d12a1bc758 tools/libxc/xc_cpufeature.h --- a/tools/libxc/xc_cpufeature.h Thu Sep 20 00:03:25 2012 +0800 +++ b/tools/libxc/xc_cpufeature.h Thu Sep 20

From 291adaf4ad6174c5641a7239c1801373e92e9975 Mon Sep 17 00:00:00 2001 From: Liu Jinsong <jinsong.liu@intel.com> Date: Thu, 28 Nov 2013 05:26:06 +0800 Subject: [PATCH v4 3/7] X86: MPX IA32_BNDCFGS msr handle When MPX supported, a new guest-state field for IA32_BNDCFGS is added to the VMCS. In addition, two new controls are added: - a VM-exit control called "clear BNDCFGS" - a

Here is the patch 0004-Enable-HLE-code-generation.patch Yours - Michael On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote: > Hi All, > > I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. > HLE from Intel TSX [2] is legacy compatible instruction set extension to > specify transactional region by adding XACQUIRE and XRELEASE prefixes. > To

Here is the patch 0002-Add-HLE-target-feature.patch Yours - Michael On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote: > Hi All, > > I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. > HLE from Intel TSX [2] is legacy compatible instruction set extension to > specify transactional region by adding XACQUIRE and XRELEASE prefixes. > To support

Here is the patch 0003-Add-XACQ-XREL-prefix-and-encoding-asm-printer-suppor.patch Yours - Michael On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote: > Hi All, > > I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. > HLE from Intel TSX [2] is legacy compatible instruction set extension to > specify transactional region by adding XACQUIRE and

Hi Michael, Why do you want to add transactional memory support to LLVM ? Can't you implement transactional memory using a library call ? Judging by the number of patches it looks like a major change to LLVM, and I am not sure that I understand the motivation for including it in LLVM. Thanks, Nadav On Feb 19, 2013, at 11:52 AM, Michael Liao <michael.liao at intel.com> wrote:

Hi All, I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order flag in __atomic_* builtins with target-specific memory model in high bits (bit 31-16 for

Hi All, I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order flag in __atomic_* builtins with target-specific memory model in high bits (bit 31-16 for

Hi, this patch passes the orginal cpuid bits for X86_FEATURE_DTES64 (64-bit DS Area) and X86_FEATURE_DSCPL (CPL Qualified Debug Store) to the guest when the BTS feature is switched on. I forgot this when I did this BTS emulation. Thanks. Dietmar. Signed-off-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com> diff -r a6b81234b189 xen/arch/x86/hvm/vmx/vpmu_core2.c ---

X86: implement PCID/INVPCID for hvm This patch handle PCID/INVPCID for hvm: For hap hvm, we enable PCID/INVPCID, since no need to intercept INVPCID, and we just set INVPCID non-root behavior as running natively; For shadow hvm, we disable PCID/INVPCID, otherwise we need to emulate INVPCID at vmm by setting INVPCID non-root behavior as vmexit. Signed-off-by: Liu, Jinsong

X86: Prepare PCID/INVPCID for hvm This patch is used to prepare exposing PCID/INVPCID features to hvm guest. The specific exposure result depend on hvm paging mode (hap/shadow), which would be handled at next patch. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> diff -r 1b62d4e08880 tools/libxc/xc_cpuid_x86.c --- a/tools/libxc/xc_cpuid_x86.c Thu Nov 17 23:09:45 2011 +0800 +++

X86: Disable PCID/INVPCID for pv This patch disable PCID/INVPCID for pv. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> diff -r 0b15aa9541dc tools/libxc/xc_cpufeature.h --- a/tools/libxc/xc_cpufeature.h Thu Nov 17 18:41:59 2011 +0800 +++ b/tools/libxc/xc_cpufeature.h Thu Nov 17 23:09:45 2011 +0800 @@ -78,6 +78,7 @@ #define X86_FEATURE_CX16 13 /* CMPXCHG16B */ #define

Nadav, I've been reading over the patches and I was wondering if you could elaborate your concerns here. I share your goal of reducing compilation time regressions for users that don't care about new feature X. From my very quick glance over the patches, I didn't see anything I couldn't opt out of. Maybe we can talk about specifics and figure out a way to make these changes not

Hi, I'm running libvert on a Debian 7 system. I have upgraded libvert and qemu from source (v1.06 and 1.5.0 respectively) and the problem persists. The guest OS is also a Debian 7 system running a non-SMP kernel. The error message from virt-manager is Error starting domain: unsupported configuration: guest and host CPU are not compatible: Host CPU does not provide required features: rtm,

On 06/13/2013 10:11 PM, Michael Giardino wrote: > Hi, > > I'm running libvert on a Debian 7 system. I have upgraded libvert and qemu > from source (v1.06 and 1.5.0 respectively) and the problem persists. The > guest OS is also a Debian 7 system running a non-SMP kernel. The error > message from virt-manager is > > Error starting domain: unsupported configuration:

Am 04.02.2016 um 17:43 schrieb Timo Sirainen: > On 04 Feb 2016, at 03:44, Thomas M?hle <thomas at bitkomplex.de> wrote: >> >> Hello, >> >> I would like to use the users password within a mail-filter script. >> Dovecots %w variable is only available within dovecot-auth, is there any >> way to access the password for a mail-filter? > > Something

Am 04.02.2016 um 20:54 schrieb Timo Sirainen: > On 04 Feb 2016, at 19:41, Thomas M?hle <thomas at bitkomplex.de> wrote: >> >> Am 04.02.2016 um 17:43 schrieb Timo Sirainen: >>> On 04 Feb 2016, at 03:44, Thomas M?hle <thomas at bitkomplex.de> wrote: >>>> >>>> Hello, >>>> >>>> I would like to use the users password

From: Yang Zhang <yang.z.zhang@Intel.com> We exposed the xsave feature to guest, but we didn''t allow guest to set CR4.OSXSAVE when guest running in nested mode. This will cause win 7 guest fail to use XP mode. In this patch, we allow guest to set CR4.OSXSAVE in nested mode when it has the xsave feature. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> ---

Dear R-help, I am working on a R package for public health surveillance where the ISO 8601 representation of dates is of importance. Especially, the ISO Week and ISO Year of a date needs to be extracted. I was quite happy to find all of this implemented in the "Date" class with appropriate calls to strptime/format (using e.g. %G and %V). However, only later I realized that this

> Am 11.05.2017 um 16:29 schrieb Leon Fauster <leonfauster at googlemail.com>: > >> Am 11.05.2017 um 14:48 schrieb Leon Fauster <leonfauster at googlemail.com>: >> >> https://access.redhat.com/support/policy/intel >> >> shows mainly Xeon CPUs. What about >> >> Intel Core i7-6700 Quad-Core Skylake >> >> has the current EL6