search for: hle

Displaying 20 results from an estimated 133 matches for "hle".

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2013 Feb 19
9
[LLVMdev] [RFC] Add Intel TSX HLE Support
Hi All, I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order flag in __atomic_* builtin...
2013 Feb 19
0
[LLVMdev] [RFC] Add Intel TSX HLE Support
Here is the patch 0004-Enable-HLE-code-generation.patch Yours - Michael On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote: > Hi All, > > I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. > HLE from Intel TSX [2] is legacy compatible instruction set extension to > specify transact...
2013 Feb 19
0
[LLVMdev] [RFC] Add Intel TSX HLE Support
Here is the patch 0002-Add-HLE-target-feature.patch Yours - Michael On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote: > Hi All, > > I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. > HLE from Intel TSX [2] is legacy compatible instruction set extension to > specify transacti...
2012 Feb 28
3
[Patch] X86: expose HLE/RTM features to dom0
X86: expose HLE/RTM features to dom0 Intel recently release 2 new features, HLE and TRM. Refer to http://software.intel.com/file/41417. This patch expose them to dom0. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> diff -r 92e03310878f xen/arch/x86/traps.c --- a/xen/arch/x86/traps.c Wed Feb 08 21:05:...
2013 Feb 19
2
[LLVMdev] [RFC] Add Intel TSX HLE Support
Hi All, I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order flag in __atomic_* builtin...
2013 Feb 19
0
[LLVMdev] [RFC] Add Intel TSX HLE Support
...? Judging by the number of patches it looks like a major change to LLVM, and I am not sure that I understand the motivation for including it in LLVM. Thanks, Nadav On Feb 19, 2013, at 11:52 AM, Michael Liao <michael.liao at intel.com> wrote: > Hi All, > > I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to > specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order > flag in __atomic...
2013 Feb 19
0
[LLVMdev] [RFC] Add Intel TSX HLE Support
Here is the patch 0003-Add-XACQ-XREL-prefix-and-encoding-asm-printer-suppor.patch Yours - Michael On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote: > Hi All, > > I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. > HLE from Intel TSX [2] is legacy compatible instruction set extension to > specify transactional region by adding XACQUIRE and XRELEASE prefixes. > To support that, GCC chooses the approach by extending the memory order > flag i...
2013 Feb 28
1
[LLVMdev] [RFC] Add Intel TSX HLE Support
...ike a major change to LLVM, and I am not sure that I understand the motivation for including it in LLVM. > > Thanks, > Nadav > > > On Feb 19, 2013, at 11:52 AM, Michael Liao <michael.liao at intel.com> wrote: > >> Hi All, >> >> I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to >> specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order >> flag in...
2013 Jun 13
3
Haswell 4770 misidentified as Sandy Bridge
...the problem persists. The guest OS is also a Debian 7 system running a non-SMP kernel. The error message from virt-manager is Error starting domain: unsupported configuration: guest and host CPU are not compatible: Host CPU does not provide required features: rtm, invpcid, erms, bmi2, smep, avx2, hle, bmi1, fsgsbase, pcid Traceback (most recent call last): File "/usr/share/virt-manager/virtManager/asyncjob.py", line 45, in cb_wrapper callback(asyncjob, *args, **kwargs) File "/usr/share/virt-manager/virtManager/asyncjob.py", line 66, in tmpcb callback(*args, **kw...
2013 Jun 17
2
Re: Fwd: Haswell 4770 misidentified as Sandy Bridge
...; guest OS is also a Debian 7 system running a non-SMP kernel. The error > message from virt-manager is > > Error starting domain: unsupported configuration: guest and host CPU are > not compatible: Host CPU does not provide required features: rtm, invpcid, > erms, bmi2, smep, avx2, hle, bmi1, fsgsbase, pcid > > Traceback (most recent call last): > File "/usr/share/virt-manager/virtManager/asyncjob.py", line 45, in > cb_wrapper > callback(asyncjob, *args, **kwargs) > File "/usr/share/virt-manager/virtManager/asyncjob.py", line 66, in...
2013 Jun 17
0
Re: Fwd: Haswell 4770 misidentified as Sandy Bridge
...op_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm ida arat epb xsaveopt pln pts dtherm tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm bogomips : 6795.58 clflush size : 64 cache_alignment : 64 address sizes : 39 bits physical, 48 bits virtual power management: processor : 1 vendor_id : GenuineIntel cpu family : 6 model : 60 model name : Intel(R) Core(TM) i7-4770 CPU @ 3.40GHz stepping : 3 microcode...
2016 Feb 04
2
user password in mail-filter plugin
Am 04.02.2016 um 17:43 schrieb Timo Sirainen: > On 04 Feb 2016, at 03:44, Thomas M?hle <thomas at bitkomplex.de> wrote: >> >> Hello, >> >> I would like to use the users password within a mail-filter script. >> Dovecots %w variable is only available within dovecot-auth, is there any >> way to access the password for a mail-filter? > > S...
2016 Feb 04
5
user password in mail-filter plugin
Am 04.02.2016 um 20:54 schrieb Timo Sirainen: > On 04 Feb 2016, at 19:41, Thomas M?hle <thomas at bitkomplex.de> wrote: >> >> Am 04.02.2016 um 17:43 schrieb Timo Sirainen: >>> On 04 Feb 2016, at 03:44, Thomas M?hle <thomas at bitkomplex.de> wrote: >>>> >>>> Hello, >>>> >>>> I would like to use the users...
2010 Jun 03
1
ISO 8601 Weeks/Years on Windows with strptime
...cability, I would like to enquire, if there are any plans to make this functionality available in Windows as well? Or are there any good workarounds to make > format.Date("2001-12-31", "%G") give "2002" instead of "" on Windows? Best regards, Michael H?hle -- > sessionInfo() R version 2.10.0 (2009-10-26) i386-pc-mingw32 locale: [1] LC_COLLATE=German_Germany.1252 LC_CTYPE=German_Germany.1252 [3] LC_MONETARY=German_Germany.1252 LC_NUMERIC=C [5] LC_TIME=German_Germany.1252 attached base packages: [1] grid stats graphics grDevices utils...
2013 Jun 13
0
Fwd: Haswell 4770 misidentified as Sandy Bridge
...the problem persists. The guest OS is also a Debian 7 system running a non-SMP kernel. The error message from virt-manager is Error starting domain: unsupported configuration: guest and host CPU are not compatible: Host CPU does not provide required features: rtm, invpcid, erms, bmi2, smep, avx2, hle, bmi1, fsgsbase, pcid Traceback (most recent call last): File "/usr/share/virt-manager/virtManager/asyncjob.py", line 45, in cb_wrapper callback(asyncjob, *args, **kwargs) File "/usr/share/virt-manager/virtManager/asyncjob.py", line 66, in tmpcb callback(*args, **kw...
2017 May 11
2
CentOS 6 / Intel CPU support
...dtes64 monitor ds_cpl vmx smx est tm2 ssse3 fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch ida arat epb xsaveopt pln pts dtherm hwp hwp_noitfy hwp_act_window hwp_epp tpr_shadow vnmi flexpriority ept vpid fsgsbase bmi1 hle avx2 smep bmi2 erms invpcid rtm rdseed adx bogomips : 6816.05 clflush size : 64 cache_alignment : 64 address sizes : 39 bits physical, 48 bits virtual power management: Linux srv-s01.ccds.de 2.6.32-696.1.1.el6.x86_64 #1 SMP Tue Apr 11 17:13:24 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux -- LF
2016 Feb 04
2
user password in mail-filter plugin
Hello, I would like to use the users password within a mail-filter script. Dovecots %w variable is only available within dovecot-auth, is there any way to access the password for a mail-filter? Thanks, Thomas
2009 Oct 16
2
Domain Joined Windows 7 and Roaming Profiles
Hello all, has anybody managed to get Windows 7 (final) to use roaming profiles? Windows 7 is joined to my Samba 3.4.1 domain and always logs me in with a temporary profile. Windows XP works without problems. Thanks for your help, Stephan -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/x-pkcs7-signature Size: 5179 bytes Desc:
2013 Dec 21
0
[Bug 72952] [NV94] no HDMI output, xrands claims DVI-D-1 disconnected
https://bugs.freedesktop.org/show_bug.cgi?id=72952 J?rg H?hle <Joerg-Cyril.Hoehle at T-Systems.com> changed: What |Removed |Added ---------------------------------------------------------------------------- Attachment #91095|0 |1 is obsolete| | --- Comment...
2004 May 06
3
Dial internal phones problem - zaphfc
...mit dem zaphfc Treiber. Jetzt hab ich folgendes Problem, habe 2 ISDN-Telefone angeschlossen. zaphfc im nt-mode. Anrufe von ausserhalb per sip (sipgate.de) kommen an. Wenn ich aber intern zwischen den zwei Telefonen (Ascom Eurit 30) sprechen m?chte geht das nur wie folgt : Erst die Nebenstelle w?hlen und dann den H?rer am Telefon abnehmen. Ich h?tte es aber gern so das ich erstmal den H?rer abnehmen kann und dann ein internen W?hlton bekomme und jetzt erst die Nebenstelle anw?hle. Ich vermute mal ich muss etwas spezielles in der extensions.conf eintragen... Hat jemand eine Idee? -- Andre...