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Liu, Jinsong

2012-Feb-28 05:10 UTC

[Patch] X86: expose HLE/RTM features to pv and hvm

X86: expose HLE/RTM features to pv and hvm

Intel recently release 2 new features, HLE and TRM.
Refer to http://software.intel.com/file/41417.
This patch expose them to pv and hvm

Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>

diff -r 8174412310fa tools/libxc/xc_cpufeature.h
--- a/tools/libxc/xc_cpufeature.h	Mon Feb 27 02:23:43 2012 +0800
+++ b/tools/libxc/xc_cpufeature.h	Mon Feb 27 03:41:13 2012 +0800
@@ -129,10 +129,12 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
 #define X86_FEATURE_FSGSBASE     0 /* {RD,WR}{FS,GS}BASE instructions */
 #define X86_FEATURE_BMI1         3 /* 1st group bit manipulation extensions */
+#define X86_FEATURE_HLE          4 /* Hardware Lock Elision */
 #define X86_FEATURE_AVX2         5 /* AVX2 instructions */
 #define X86_FEATURE_SMEP         7 /* Supervisor Mode Execution Protection */
 #define X86_FEATURE_BMI2         8 /* 2nd group bit manipulation extensions */
 #define X86_FEATURE_ERMS         9 /* Enhanced REP MOVSB/STOSB */
 #define X86_FEATURE_INVPCID     10 /* Invalidate Process Context ID */
+#define X86_FEATURE_RTM         11 /* Restricted Transactional Memory */
 
 #endif /* __LIBXC_CPUFEATURE_H */
diff -r 8174412310fa tools/libxc/xc_cpuid_x86.c
--- a/tools/libxc/xc_cpuid_x86.c	Mon Feb 27 02:23:43 2012 +0800
+++ b/tools/libxc/xc_cpuid_x86.c	Mon Feb 27 03:41:13 2012 +0800
@@ -362,11 +362,13 @@
     case 0x00000007: /* Intel-defined CPU features */
         if ( input[1] == 0 ) {
             regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
+                        bitmaskof(X86_FEATURE_HLE)  |
                         bitmaskof(X86_FEATURE_AVX2) |
                         bitmaskof(X86_FEATURE_SMEP) |
                         bitmaskof(X86_FEATURE_BMI2) |
                         bitmaskof(X86_FEATURE_ERMS) |
                         bitmaskof(X86_FEATURE_INVPCID) |
+                        bitmaskof(X86_FEATURE_RTM)  |
                         bitmaskof(X86_FEATURE_FSGSBASE));
         } else
             regs[1] = 0;
@@ -495,9 +497,11 @@
     case 0x00000007:
         if ( input[1] == 0 )
             regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
+                        bitmaskof(X86_FEATURE_HLE)  |
                         bitmaskof(X86_FEATURE_AVX2) |
                         bitmaskof(X86_FEATURE_BMI2) |
                         bitmaskof(X86_FEATURE_ERMS) |
+                        bitmaskof(X86_FEATURE_RTM)  |
                         bitmaskof(X86_FEATURE_FSGSBASE));
         else
             regs[1] = 0;

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Liu, Jinsong

2012-Mar-01 11:23 UTC

head link

Re: [Patch] X86: expose HLE/RTM features to pv and hvm

Ian,

any comments?

Thanks,
Jinsong


Liu, Jinsong wrote:> X86: expose HLE/RTM features to pv and hvm
> 
> Intel recently release 2 new features, HLE and TRM.
> Refer to http://software.intel.com/file/41417.
> This patch expose them to pv and hvm
> 
> Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
> 
> diff -r 8174412310fa tools/libxc/xc_cpufeature.h
> --- a/tools/libxc/xc_cpufeature.h	Mon Feb 27 02:23:43 2012 +0800
> +++ b/tools/libxc/xc_cpufeature.h	Mon Feb 27 03:41:13 2012 +0800
> @@ -129,10 +129,12 @@
>  /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
>  #define X86_FEATURE_FSGSBASE     0 /* {RD,WR}{FS,GS}BASE
>  instructions */ #define X86_FEATURE_BMI1         3 /* 1st group bit
> manipulation extensions */ +#define X86_FEATURE_HLE          4 /*
>  Hardware Lock Elision */ #define X86_FEATURE_AVX2         5 /* AVX2
>  instructions */ #define X86_FEATURE_SMEP         7 /* Supervisor
>  Mode Execution Protection */ #define X86_FEATURE_BMI2         8 /*
>  2nd group bit manipulation extensions */ #define X86_FEATURE_ERMS   
>  9 /* Enhanced REP MOVSB/STOSB */ #define X86_FEATURE_INVPCID     10
> /* Invalidate Process Context ID */ +#define X86_FEATURE_RTM        
> 11 /* Restricted Transactional Memory */ 
> 
>  #endif /* __LIBXC_CPUFEATURE_H */
> diff -r 8174412310fa tools/libxc/xc_cpuid_x86.c
> --- a/tools/libxc/xc_cpuid_x86.c	Mon Feb 27 02:23:43 2012 +0800
> +++ b/tools/libxc/xc_cpuid_x86.c	Mon Feb 27 03:41:13 2012 +0800
> @@ -362,11 +362,13 @@
>      case 0x00000007: /* Intel-defined CPU features */
>          if ( input[1] == 0 ) {
>              regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
> +                        bitmaskof(X86_FEATURE_HLE)  |
>                          bitmaskof(X86_FEATURE_AVX2) |
>                          bitmaskof(X86_FEATURE_SMEP) |
>                          bitmaskof(X86_FEATURE_BMI2) |
>                          bitmaskof(X86_FEATURE_ERMS) |
>                          bitmaskof(X86_FEATURE_INVPCID) |
> +                        bitmaskof(X86_FEATURE_RTM)  |
>                          bitmaskof(X86_FEATURE_FSGSBASE));
>          } else
>              regs[1] = 0;
> @@ -495,9 +497,11 @@
>      case 0x00000007:
>          if ( input[1] == 0 )
>              regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
> +                        bitmaskof(X86_FEATURE_HLE)  |
>                          bitmaskof(X86_FEATURE_AVX2) |
>                          bitmaskof(X86_FEATURE_BMI2) |
>                          bitmaskof(X86_FEATURE_ERMS) |
> +                        bitmaskof(X86_FEATURE_RTM)  |
>                          bitmaskof(X86_FEATURE_FSGSBASE));
>          else
>              regs[1] = 0;


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Xen-devel@lists.xen.org
http://lists.xen.org/xen-devel

Keir Fraser

2012-Mar-01 11:33 UTC

head link

Re: [Patch] X86: expose HLE/RTM features to pv and hvm

I''ll apply this one shortly.

 K.

On 01/03/2012 11:23, "Liu, Jinsong" <jinsong.liu@intel.com>
wrote:
> Ian,
> 
> any comments?
> 
> Thanks,
> Jinsong
> 
> 
> Liu, Jinsong wrote:
>> X86: expose HLE/RTM features to pv and hvm
>> 
>> Intel recently release 2 new features, HLE and TRM.
>> Refer to http://software.intel.com/file/41417.
>> This patch expose them to pv and hvm
>> 
>> Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
>> 
>> diff -r 8174412310fa tools/libxc/xc_cpufeature.h
>> --- a/tools/libxc/xc_cpufeature.h Mon Feb 27 02:23:43 2012 +0800
>> +++ b/tools/libxc/xc_cpufeature.h Mon Feb 27 03:41:13 2012 +0800
>> @@ -129,10 +129,12 @@
>>  /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
>>  #define X86_FEATURE_FSGSBASE     0 /* {RD,WR}{FS,GS}BASE
>>  instructions */ #define X86_FEATURE_BMI1         3 /* 1st group bit
>> manipulation extensions */ +#define X86_FEATURE_HLE          4 /*
>>  Hardware Lock Elision */ #define X86_FEATURE_AVX2         5 /* AVX2
>>  instructions */ #define X86_FEATURE_SMEP         7 /* Supervisor
>>  Mode Execution Protection */ #define X86_FEATURE_BMI2         8 /*
>>  2nd group bit manipulation extensions */ #define X86_FEATURE_ERMS
>>  9 /* Enhanced REP MOVSB/STOSB */ #define X86_FEATURE_INVPCID     10
>> /* Invalidate Process Context ID */ +#define X86_FEATURE_RTM
>> 11 /* Restricted Transactional Memory */
>> 
>>  #endif /* __LIBXC_CPUFEATURE_H */
>> diff -r 8174412310fa tools/libxc/xc_cpuid_x86.c
>> --- a/tools/libxc/xc_cpuid_x86.c Mon Feb 27 02:23:43 2012 +0800
>> +++ b/tools/libxc/xc_cpuid_x86.c Mon Feb 27 03:41:13 2012 +0800
>> @@ -362,11 +362,13 @@
>>      case 0x00000007: /* Intel-defined CPU features */
>>          if ( input[1] == 0 ) {
>>              regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
>> +                        bitmaskof(X86_FEATURE_HLE)  |
>>                          bitmaskof(X86_FEATURE_AVX2) |
>>                          bitmaskof(X86_FEATURE_SMEP) |
>>                          bitmaskof(X86_FEATURE_BMI2) |
>>                          bitmaskof(X86_FEATURE_ERMS) |
>>                          bitmaskof(X86_FEATURE_INVPCID) |
>> +                        bitmaskof(X86_FEATURE_RTM)  |
>>                          bitmaskof(X86_FEATURE_FSGSBASE));
>>          } else
>>              regs[1] = 0;
>> @@ -495,9 +497,11 @@
>>      case 0x00000007:
>>          if ( input[1] == 0 )
>>              regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
>> +                        bitmaskof(X86_FEATURE_HLE)  |
>>                          bitmaskof(X86_FEATURE_AVX2) |
>>                          bitmaskof(X86_FEATURE_BMI2) |
>>                          bitmaskof(X86_FEATURE_ERMS) |
>> +                        bitmaskof(X86_FEATURE_RTM)  |
>>                          bitmaskof(X86_FEATURE_FSGSBASE));
>>          else
>>              regs[1] = 0;
>

Liu, Jinsong

2012-Mar-01 11:45 UTC

head link

Re: [Patch] X86: expose HLE/RTM features to pv and hvm

Thanks a lot!

Jinsong

Keir Fraser wrote:> I''ll apply this one shortly.
> 
>  K.
> 
> On 01/03/2012 11:23, "Liu, Jinsong" <jinsong.liu@intel.com>
wrote:
> 
>> Ian,
>> 
>> any comments?
>> 
>> Thanks,
>> Jinsong
>> 
>> 
>> Liu, Jinsong wrote:
>>> X86: expose HLE/RTM features to pv and hvm
>>> 
>>> Intel recently release 2 new features, HLE and TRM.
>>> Refer to http://software.intel.com/file/41417.
>>> This patch expose them to pv and hvm
>>> 
>>> Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
>>> 
>>> diff -r 8174412310fa tools/libxc/xc_cpufeature.h
>>> --- a/tools/libxc/xc_cpufeature.h Mon Feb 27 02:23:43 2012 +0800
>>> +++ b/tools/libxc/xc_cpufeature.h Mon Feb 27 03:41:13 2012 +0800 @@
>>>  -129,10 +129,12 @@ /* Intel-defined CPU features, CPUID level
>>>  0x00000007:0 (ebx) */ #define X86_FEATURE_FSGSBASE     0 /*
>>>  {RD,WR}{FS,GS}BASE instructions */ #define X86_FEATURE_BMI1       
>>> 3 /* 1st group bit manipulation extensions */ +#define
>>>  X86_FEATURE_HLE          4 /* Hardware Lock Elision */ #define
>>>  X86_FEATURE_AVX2         5 /* AVX2 instructions */ #define
>>>  X86_FEATURE_SMEP         7 /* Supervisor Mode Execution Protection
>>>  */ #define X86_FEATURE_BMI2         8 /* 2nd group bit
>>>  manipulation extensions */ #define X86_FEATURE_ERMS 9 /* Enhanced
>>> REP MOVSB/STOSB */ #define X86_FEATURE_INVPCID     10 /* Invalidate
>>> Process Context ID */ +#define X86_FEATURE_RTM 11 /* Restricted
>>> Transactional Memory */ 
>>> 
>>>  #endif /* __LIBXC_CPUFEATURE_H */
>>> diff -r 8174412310fa tools/libxc/xc_cpuid_x86.c
>>> --- a/tools/libxc/xc_cpuid_x86.c Mon Feb 27 02:23:43 2012 +0800
>>> +++ b/tools/libxc/xc_cpuid_x86.c Mon Feb 27 03:41:13 2012 +0800 @@
>>>      -362,11 +362,13 @@ case 0x00000007: /* Intel-defined CPU
>>>          features */ if ( input[1] == 0 ) {
>>>              regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
>>> +                        bitmaskof(X86_FEATURE_HLE)  |
>>>                          bitmaskof(X86_FEATURE_AVX2) |
>>>                          bitmaskof(X86_FEATURE_SMEP) |
>>>                          bitmaskof(X86_FEATURE_BMI2) |
>>>                          bitmaskof(X86_FEATURE_ERMS) |
>>>                          bitmaskof(X86_FEATURE_INVPCID) |
>>> +                        bitmaskof(X86_FEATURE_RTM)  |
>>>                          bitmaskof(X86_FEATURE_FSGSBASE));         
>>>              } else regs[1] = 0;
>>> @@ -495,9 +497,11 @@
>>>      case 0x00000007:
>>>          if ( input[1] == 0 )
>>>              regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
>>> +                        bitmaskof(X86_FEATURE_HLE)  |
>>>                          bitmaskof(X86_FEATURE_AVX2) |
>>>                          bitmaskof(X86_FEATURE_BMI2) |
>>>                          bitmaskof(X86_FEATURE_ERMS) |
>>> +                        bitmaskof(X86_FEATURE_RTM)  |
>>>                          bitmaskof(X86_FEATURE_FSGSBASE));         
>>>              else regs[1] = 0;

Ian Jackson

2012-Mar-01 12:55 UTC

head link

Re: [Patch] X86: expose HLE/RTM features to pv and hvm

Keir Fraser writes ("Re: [Patch] X86: expose HLE/RTM features to pv and
hvm"):> I''ll apply this one shortly.
Thanks.  I''m always a bit unsure about these, without reading the
processor manuals...

Ian.

Konrad Rzeszutek Wilk

2012-Mar-12 18:06 UTC

head link

Re: [Patch] X86: expose HLE/RTM features to pv and hvm

On Tue, Feb 28, 2012 at 05:10:55AM +0000, Liu, Jinsong
wrote:> X86: expose HLE/RTM features to pv and hvm
> 
> Intel recently release 2 new features, HLE and TRM.
> Refer to http://software.intel.com/file/41417.
> This patch expose them to pv and hvm
Should this be also exposed to Dom0?
> 
> Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
> 
> diff -r 8174412310fa tools/libxc/xc_cpufeature.h
> --- a/tools/libxc/xc_cpufeature.h	Mon Feb 27 02:23:43 2012 +0800
> +++ b/tools/libxc/xc_cpufeature.h	Mon Feb 27 03:41:13 2012 +0800
> @@ -129,10 +129,12 @@
>  /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
>  #define X86_FEATURE_FSGSBASE     0 /* {RD,WR}{FS,GS}BASE instructions */
>  #define X86_FEATURE_BMI1         3 /* 1st group bit manipulation
extensions */
> +#define X86_FEATURE_HLE          4 /* Hardware Lock Elision */
>  #define X86_FEATURE_AVX2         5 /* AVX2 instructions */
>  #define X86_FEATURE_SMEP         7 /* Supervisor Mode Execution Protection
*/
>  #define X86_FEATURE_BMI2         8 /* 2nd group bit manipulation
extensions */
>  #define X86_FEATURE_ERMS         9 /* Enhanced REP MOVSB/STOSB */
>  #define X86_FEATURE_INVPCID     10 /* Invalidate Process Context ID */
> +#define X86_FEATURE_RTM         11 /* Restricted Transactional Memory */
>  
>  #endif /* __LIBXC_CPUFEATURE_H */
> diff -r 8174412310fa tools/libxc/xc_cpuid_x86.c
> --- a/tools/libxc/xc_cpuid_x86.c	Mon Feb 27 02:23:43 2012 +0800
> +++ b/tools/libxc/xc_cpuid_x86.c	Mon Feb 27 03:41:13 2012 +0800
> @@ -362,11 +362,13 @@
>      case 0x00000007: /* Intel-defined CPU features */
>          if ( input[1] == 0 ) {
>              regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
> +                        bitmaskof(X86_FEATURE_HLE)  |
>                          bitmaskof(X86_FEATURE_AVX2) |
>                          bitmaskof(X86_FEATURE_SMEP) |
>                          bitmaskof(X86_FEATURE_BMI2) |
>                          bitmaskof(X86_FEATURE_ERMS) |
>                          bitmaskof(X86_FEATURE_INVPCID) |
> +                        bitmaskof(X86_FEATURE_RTM)  |
>                          bitmaskof(X86_FEATURE_FSGSBASE));
>          } else
>              regs[1] = 0;
> @@ -495,9 +497,11 @@
>      case 0x00000007:
>          if ( input[1] == 0 )
>              regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
> +                        bitmaskof(X86_FEATURE_HLE)  |
>                          bitmaskof(X86_FEATURE_AVX2) |
>                          bitmaskof(X86_FEATURE_BMI2) |
>                          bitmaskof(X86_FEATURE_ERMS) |
> +                        bitmaskof(X86_FEATURE_RTM)  |
>                          bitmaskof(X86_FEATURE_FSGSBASE));
>          else
>              regs[1] = 0;
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xen.org
> http://lists.xen.org/xen-devel

Liu, Jinsong

2012-Mar-13 01:16 UTC

head link

Re: [Patch] X86: expose HLE/RTM features to pv and hvm

Konrad Rzeszutek Wilk wrote:> On Tue, Feb 28, 2012 at 05:10:55AM +0000, Liu, Jinsong wrote:
>> X86: expose HLE/RTM features to pv and hvm
>> 
>> Intel recently release 2 new features, HLE and TRM.
>> Refer to http://software.intel.com/file/41417.
>> This patch expose them to pv and hvm
> 
> Should this be also exposed to Dom0?
> 
Yes, and it has been done in c/s 24893 at xen side.

Thanks,
Jinsong
>> 
>> Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
>> 
>> diff -r 8174412310fa tools/libxc/xc_cpufeature.h
>> --- a/tools/libxc/xc_cpufeature.h	Mon Feb 27 02:23:43 2012 +0800
>> +++ b/tools/libxc/xc_cpufeature.h	Mon Feb 27 03:41:13 2012 +0800 @@
>>  -129,10 +129,12 @@ /* Intel-defined CPU features, CPUID level
>>  0x00000007:0 (ebx) */ #define X86_FEATURE_FSGSBASE     0 /*
>>  {RD,WR}{FS,GS}BASE instructions */ #define X86_FEATURE_BMI1        
>> 3 /* 1st group bit manipulation extensions */ +#define
>>  X86_FEATURE_HLE          4 /* Hardware Lock Elision */ #define
>>  X86_FEATURE_AVX2         5 /* AVX2 instructions */ #define
>>  X86_FEATURE_SMEP         7 /* Supervisor Mode Execution Protection
>>  */ #define X86_FEATURE_BMI2         8 /* 2nd group bit manipulation
>>  extensions */ #define X86_FEATURE_ERMS         9 /* Enhanced REP
>> MOVSB/STOSB */ #define X86_FEATURE_INVPCID     10 /* Invalidate
>> Process Context ID */ +#define X86_FEATURE_RTM         11 /*
>> Restricted Transactional Memory */  
>> 
>>  #endif /* __LIBXC_CPUFEATURE_H */
>> diff -r 8174412310fa tools/libxc/xc_cpuid_x86.c
>> --- a/tools/libxc/xc_cpuid_x86.c	Mon Feb 27 02:23:43 2012 +0800
>> +++ b/tools/libxc/xc_cpuid_x86.c	Mon Feb 27 03:41:13 2012 +0800 @@
>>      -362,11 +362,13 @@ case 0x00000007: /* Intel-defined CPU
>>          features */ if ( input[1] == 0 ) {
>>              regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
>> +                        bitmaskof(X86_FEATURE_HLE)  |
>>                          bitmaskof(X86_FEATURE_AVX2) |
>>                          bitmaskof(X86_FEATURE_SMEP) |
>>                          bitmaskof(X86_FEATURE_BMI2) |
>>                          bitmaskof(X86_FEATURE_ERMS) |
>>                          bitmaskof(X86_FEATURE_INVPCID) |
>> +                        bitmaskof(X86_FEATURE_RTM)  |
>>                          bitmaskof(X86_FEATURE_FSGSBASE));         
>>              } else regs[1] = 0;
>> @@ -495,9 +497,11 @@
>>      case 0x00000007:
>>          if ( input[1] == 0 )
>>              regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
>> +                        bitmaskof(X86_FEATURE_HLE)  |
>>                          bitmaskof(X86_FEATURE_AVX2) |
>>                          bitmaskof(X86_FEATURE_BMI2) |
>>                          bitmaskof(X86_FEATURE_ERMS) |
>> +                        bitmaskof(X86_FEATURE_RTM)  |
>>                          bitmaskof(X86_FEATURE_FSGSBASE));         
>>              else regs[1] = 0;
> 
> 
>> _______________________________________________
>> Xen-devel mailing list
>> Xen-devel@lists.xen.org
>> http://lists.xen.org/xen-devel

Xen devel - Feb 2012 - [Patch] X86: expose HLE/RTM features to pv and hvm

[Patch] X86: expose HLE/RTM features to pv and hvm

Re: [Patch] X86: expose HLE/RTM features to pv and hvm

Re: [Patch] X86: expose HLE/RTM features to pv and hvm

Re: [Patch] X86: expose HLE/RTM features to pv and hvm

Re: [Patch] X86: expose HLE/RTM features to pv and hvm

Re: [Patch] X86: expose HLE/RTM features to pv and hvm

Re: [Patch] X86: expose HLE/RTM features to pv and hvm