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You might find this useful ... TSC and Power Management Events on AMD Processors - Nov 2, 2005 - Rich Brunner, AMD Fellow Current AMD Opteron(tm) and Athlon(tm)64 processors provide power management mechanisms that independently adjust the performance state ("P-state") and power state ("C-state") of the p...

...1756==XRay: Log file in 'xray-log.fdr-mode.Xubrrm' Flush status 2 henry at OptiPlex-9010:~/build_xray/llvm-instrumented-build/bin$ ./llvm-xray convert -f yaml -symbolize -instr_map=./fdr-mode xray-log.fdr-mode.Xubrrm --- header: version: 2 type: 1 constant-tsc: true nonstop-tsc: true cycle-frequency: 3400000000 records: - { type: 0, func-id: 3, function: 'fA()', cpu: 2, thread: 31756, kind: function-enter, tsc: 4955892956329578 } - { type: 0, func-id: 2, function: 'fB()', cpu: 2, thread: 31756, kind: function-enter, ts...

>From /xen-unstable.hg/xen/arch/x86/cpu/intel.c if ((c->x86 == 0xf && c->x86_model >= 0x03) || (c->x86 == 0x6 && c->x86_model >= 0x0e)) set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); if (cpuid_edx(0x80000007) & (1u<<8)) { set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability); set_bit(X86_FEATURE_TSC_RELIABLE, c->x86_capability); } I am trying to determine the difference betwe...

Intel recently release a new tsc adjust feature at latest SDM 17.13.3. CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported. Basically it is used to simplify TSC synchronization, operation of IA32_TSC_ADJUST MSR is as follows: 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; 2). If an execution of WRMSR to the IA...

Various versions of Linux under various circumstances select TSC as the primary clocksource for the kernel. This is especially true for uniprocessor kernels, but also in some cases for multiprocessor kernels. In most cases, this is because a processor bit (tsc_invariant? constant_tsc?) is passed through directly from the hardware via Xen and tested by the hvm...

...> writes: > On Wed, Oct 03, 2018 at 11:22:58AM +0200, Vitaly Kuznetsov wrote: >> >> There is a very long history of different (hardware) issues Marcelo was >> fighting with and the current code is the survived Frankenstein. > > Right, the code has to handle different TSC modes. > >> E.g. it >> is very, very unclear what "catchup", "always catchup" and >> masterclock-less mode in general are and if we still need them. > > Catchup means handling exposed (to guest) TSC frequency smaller than > HW TSC frequency. > &...

...> writes: > On Wed, Oct 03, 2018 at 11:22:58AM +0200, Vitaly Kuznetsov wrote: >> >> There is a very long history of different (hardware) issues Marcelo was >> fighting with and the current code is the survived Frankenstein. > > Right, the code has to handle different TSC modes. > >> E.g. it >> is very, very unclear what "catchup", "always catchup" and >> masterclock-less mode in general are and if we still need them. > > Catchup means handling exposed (to guest) TSC frequency smaller than > HW TSC frequency. > &...

> Date: Fri, 17 Feb 2012 12:06:05 +0000 > From: Ian Campbell <Ian.Campbell@citrix.com> > To: Qrux <qrux.qed@gmail.com> > Cc: "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com> > Subject: Re: [Xen-devel] Xen domU Timekeeping (a.k.a TSC/HPET issues) > Message-ID: <1329480365.3131.50.camel@zakaz.uk.xensource.com> > Content-Type: text/plain; charset="UTF-8" > > I''m afraid I don''t know the answer to most of your questions (hence I''m > afraid I''ve trimmed the quotes ra...

...kvm/x86.c. And the purpose of > that code is very, very opaque. > > Can one of you explain what the code is even doing? From a couple of > attempts to read through it, it's a whole bunch of > probably-extremely-buggy code that, drumroll please, tries to > atomically read the TSC value and the time. And decide whether the > result is "based on the TSC". And then synthesizes a TSC-to-ns > multiplier and shift, based on *something other than the actual > multiply and shift used*. > > IOW, unless I'm totally misunderstanding it, the code digs int...

...kvm/x86.c. And the purpose of > that code is very, very opaque. > > Can one of you explain what the code is even doing? From a couple of > attempts to read through it, it's a whole bunch of > probably-extremely-buggy code that, drumroll please, tries to > atomically read the TSC value and the time. And decide whether the > result is "based on the TSC". And then synthesizes a TSC-to-ns > multiplier and shift, based on *something other than the actual > multiply and shift used*. > > IOW, unless I'm totally misunderstanding it, the code digs int...

Fix virtual apic irq distribution. But currently we inject PIT irqs to cpu0 only. Also mute some warning messages. Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com> Signed-off-by: Xin Li <xin.b.li@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Lguest currently requires a TSC, which breaks older machines and Matt Mackall who boots the host with "notsc". In addition, there is no good solution to changing TSC speeds (informing all the guests about the TSC impending change before it happens would be a great deal of code and have issues with disobedient guests)....

Lguest currently requires a TSC, which breaks older machines and Matt Mackall who boots the host with "notsc". In addition, there is no good solution to changing TSC speeds (informing all the guests about the TSC impending change before it happens would be a great deal of code and have issues with disobedient guests)....

...t 4, 2018, at 1:11 AM, Peter Zijlstra <peterz at infradead.org> wrote: > >> On Thu, Oct 04, 2018 at 09:54:45AM +0200, Vitaly Kuznetsov wrote: >> I was hoping to hear this from you :-) If I am to suggest how we can >> move forward I'd propose: >> - Check if pure TSC can be used on SkyLake+ systems (where TSC scaling >> is supported). >> - Check if non-masterclock mode is still needed. E.g. HyperV's TSC page >> clocksource is a single page for the whole VM, not a per-cpu thing. Can >> we think that all the buggy hardware is already g...

...t 4, 2018, at 1:11 AM, Peter Zijlstra <peterz at infradead.org> wrote: > >> On Thu, Oct 04, 2018 at 09:54:45AM +0200, Vitaly Kuznetsov wrote: >> I was hoping to hear this from you :-) If I am to suggest how we can >> move forward I'd propose: >> - Check if pure TSC can be used on SkyLake+ systems (where TSC scaling >> is supported). >> - Check if non-masterclock mode is still needed. E.g. HyperV's TSC page >> clocksource is a single page for the whole VM, not a per-cpu thing. Can >> we think that all the buggy hardware is already g...

Implement tsc adjust feature IA32_TSC_ADJUST MSR is maintained separately for each logical processor. A logical processor maintains and uses the IA32_TSC_ADJUST MSR as follows: 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or subtr...

Dear All, I have downloaded CentOS 7.2.1511 DVD and tried to install it on a new laptop that comes with an Intel i7 6th generation processor and don't matter which option I use (install, test media or troubleshooting); I get the following error: [ 0.000000] tsc: Fast TSC calibration failed [ 0.321345] pnp 00:0d: can't evaluate _CRS: 1 At this time I am not able to use any keys on the keyboard; therefore, the only option I have is to power the laptop off. The laptop specifications are as follow: Processor : Intel Core i7-6700HQ 2.6GHz (Turbo up to 3....

Hi, I am trying to correlating performance issue in guest VM with the scheduling trace from Xentrace. User-mode application in guest VM periodically dump APIC ID and RDTSC into trace. I also start Xentrace in Dom0 during the same period. However, I notice that range of TSC values report both trace is completely disjointed. TSC values from Xentrace is always greater than what guest VM see, even if I start capturing Xen''s trace 30s before capturing trace in...

...t;peterz at infradead.org> wrote: >>> >>>> On Thu, Oct 04, 2018 at 09:54:45AM +0200, Vitaly Kuznetsov wrote: >>>> I was hoping to hear this from you :-) If I am to suggest how we can >>>> move forward I'd propose: >>>> - Check if pure TSC can be used on SkyLake+ systems (where TSC scaling >>>> is supported). >>>> - Check if non-masterclock mode is still needed. E.g. HyperV's TSC page >>>> clocksource is a single page for the whole VM, not a per-cpu thing. Can >>>> we think that all...

...t;peterz at infradead.org> wrote: >>> >>>> On Thu, Oct 04, 2018 at 09:54:45AM +0200, Vitaly Kuznetsov wrote: >>>> I was hoping to hear this from you :-) If I am to suggest how we can >>>> move forward I'd propose: >>>> - Check if pure TSC can be used on SkyLake+ systems (where TSC scaling >>>> is supported). >>>> - Check if non-masterclock mode is still needed. E.g. HyperV's TSC page >>>> clocksource is a single page for the whole VM, not a per-cpu thing. Can >>>> we think that all...