search for: x86_feature_smep

The first and third patches are cleaned up versions of an earlier v3 submission by Yang. 1: Nested VMX: check VMX capability before read VMX related MSRs 2: VMX: clean up capability checks 3: Nested VMX: fix IA32_VMX_CR4_FIXED1 msr emulation 4: x86: make hvm_cpuid() tolerate NULL pointers Signed-off-by: Jan Beulich <jbeulich@suse.com>

...*/ +#define X86_FEATURE_PCID 17 /* Process Context ID */ #define X86_FEATURE_DCA 18 /* Direct Cache Access */ #define X86_FEATURE_SSE4_1 19 /* Streaming SIMD Extensions 4.1 */ #define X86_FEATURE_SSE4_2 20 /* Streaming SIMD Extensions 4.2 */ @@ -132,5 +133,6 @@ #define X86_FEATURE_SMEP 7 /* Supervisor Mode Execution Protection */ #define X86_FEATURE_BMI2 8 /* 2nd group bit manipulation extensions */ #define X86_FEATURE_ERMS 9 /* Enhanced REP MOVSB/STOSB */ +#define X86_FEATURE_INVPCID 10 /* Invalidate Process Context ID */ #endif /* __LIBXC_CPUFEA...

...| + bitmaskof(X86_FEATURE_PCID) | bitmaskof(X86_FEATURE_SSE4_1) | bitmaskof(X86_FEATURE_SSE4_2) | bitmaskof(X86_FEATURE_MOVBE) | @@ -363,6 +364,7 @@ static void xc_cpuid_hvm_policy( bitmaskof(X86_FEATURE_SMEP) | bitmaskof(X86_FEATURE_BMI2) | bitmaskof(X86_FEATURE_ERMS) | + bitmaskof(X86_FEATURE_INVPCID) | bitmaskof(X86_FEATURE_FSGSBASE)); } else regs[1] = 0; __________________________...

...p;= (bitmaskof(X86_FEATURE_BMI1) | + regs[1] &= (bitmaskof(X86_FEATURE_TSC_ADJUST) | + bitmaskof(X86_FEATURE_BMI1) | bitmaskof(X86_FEATURE_HLE) | bitmaskof(X86_FEATURE_AVX2) | bitmaskof(X86_FEATURE_SMEP) | _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel

...xen/arch/x86/hvm/hvm.c index 9c88c73..0f7178b 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -2905,6 +2905,12 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, if ( (count == 0) && !cpu_has_smep ) *ebx &= ~cpufeat_mask(X86_FEATURE_SMEP); + /* Don''t expose MPX to hvm when VMX support is not available */ + if ( (count == 0) && + (!(vmx_vmexit_control & VM_EXIT_CLEAR_BNDCFGS) || + !(vmx_vmentry_control & VM_ENTRY_LOAD_BNDCFGS)) ) + *ebx &= ~cpufeat_mask...

...bx), word 7 */ #define X86_FEATURE_FSGSBASE (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */ #define X86_FEATURE_BMI1 (7*32+ 3) /* 1st bit manipulation extensions */ +#define X86_FEATURE_HLE (7*32+ 4) /* Hardware Lock Elision */ #define X86_FEATURE_AVX2 (7*32+ 5) /* AVX2 instructions */ #define X86_FEATURE_SMEP (7*32+ 7) /* Supervisor Mode Execution Protection */ #define X86_FEATURE_BMI2 (7*32+ 8) /* 2nd bit manipulation extensions */ #define X86_FEATURE_ERMS (7*32+ 9) /* Enhanced REP MOVSB/STOSB */ #define X86_FEATURE_INVPCID (7*32+10) /* Invalidate Process Context ID */ +#define X86_FEATURE_RTM (7*3...

...pufeat_mask(X86_FEATURE_OSXSAVE) : 0; + + /* Not expose PCID to non-hap hvm */ + if ( !hap_enabled(d) ) + *ecx &= ~cpufeat_mask(X86_FEATURE_PCID); break; case 0x7: if ( (count == 0) && !cpu_has_smep ) *ebx &= ~cpufeat_mask(X86_FEATURE_SMEP); + + /* Not expose INVPCID to non-hap hvm */ + if ( (count == 0) && !hap_enabled(d) ) + *ebx &= ~cpufeat_mask(X86_FEATURE_INVPCID); break; case 0xb: /* Fix the x2APIC identifier. */ diff -r c61a5ba8c972 xen/arch/x86/hvm/vmx/vmcs.c --- a/x...

The first patch really isn''t as much of a follow-up than what triggered the security issues to be noticed in the first place. 1: x86: preserve FPU selectors for 32-bit guest code 2: x86: fix XCR0 handling 3: x86/xsave: adjust state management 4: x86/fxsave: bring in line with recent xsave adjustments The first two I would see as candidates for 4.3 (as well as subsequent backporting,