similar to: [PATCH 3/3] Expose tsc adjust to hvm guest

X86: expose HLE/RTM features to dom0 Intel recently release 2 new features, HLE and TRM. Refer to http://software.intel.com/file/41417. This patch expose them to dom0. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> diff -r 92e03310878f xen/arch/x86/traps.c --- a/xen/arch/x86/traps.c Wed Feb 08 21:05:52 2012 +0800 +++ b/xen/arch/x86/traps.c Mon Feb 27 02:23:42 2012 +0800 @@ -857,9

X86: Prepare PCID/INVPCID for hvm This patch is used to prepare exposing PCID/INVPCID features to hvm guest. The specific exposure result depend on hvm paging mode (hap/shadow), which would be handled at next patch. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> diff -r 1b62d4e08880 tools/libxc/xc_cpuid_x86.c --- a/tools/libxc/xc_cpuid_x86.c Thu Nov 17 23:09:45 2011 +0800 +++

X86: Disable PCID/INVPCID for pv This patch disable PCID/INVPCID for pv. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> diff -r 0b15aa9541dc tools/libxc/xc_cpufeature.h --- a/tools/libxc/xc_cpufeature.h Thu Nov 17 18:41:59 2011 +0800 +++ b/tools/libxc/xc_cpufeature.h Thu Nov 17 23:09:45 2011 +0800 @@ -78,6 +78,7 @@ #define X86_FEATURE_CX16 13 /* CMPXCHG16B */ #define

- use __clear_bit() rather than clear_bit() - use switch statements instead of long series of if-s - eliminate pointless casts (Applies cleanly only on top of the previously sent SVM/EFER patch.) Signed-off-by: Jan Beulich <jbeulich@novell.com> Index: 2007-08-08/xen/arch/x86/hvm/hvm.c =================================================================== ---

Intel recently release a new tsc adjust feature at latest SDM 17.13.3. CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported. Basically it is used to simplify TSC synchronization, operation of IA32_TSC_ADJUST MSR is as follows: 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or subtracts) value X from the

Hello, I encountered the following bug when migrating a Linux-2.6.32.54 PV domain on Xen-3.4.3 between different hosts, whose uptime differs by several minutes (3 hosts, each ~5 minutes apart): When migrating from a host with lower uptime to a host with higher uptime, the VM looses it''s network connection for some time and then continues after some minutes (roughly equivalent to the

Hi, I am trying to correlating performance issue in guest VM with the scheduling trace from Xentrace. User-mode application in guest VM periodically dump APIC ID and RDTSC into trace. I also start Xentrace in Dom0 during the same period. However, I notice that range of TSC values report both trace is completely disjointed. TSC values from Xentrace is always greater than what guest VM see, even

ACPI C2 is quite possible mapped to CPU C3 or deeper state, so thinking from worst cases, enable C3 like entry/exit handling for C2 by default. Option ''lapic_timer_c2_ok'' can be used to select simple C2 entry/exit only if the user make sure that LAPIC tmr & TSC will not be stopped during C2. Signed-off-by: Wei Gang <gang.wei@intel.com>

Host S3 implicitly resets the host TSC to 0, but the tsc offset for hvm domains is not recalculated when they resume, causing it to go into negative values. In Linux guest using tsc clocksource, this results in a hang after wrap back to positive values since the tsc clocksource implementation expects it reset. Signed-off-by: Tomasz Wroblewski <tomasz.wroblewski@citrix.com> ---

This patch just changes a couple of KERN_INFO printk's so that they always print on boot. These printk's report whether or not xen believes the TSC's are synchronized across all processors. I wish I knew this code was here as it could have been used several times to help diagnose problems, but it would be even better if it didn't require the loglvl=info boot option to see it.

If we use SIFC to upload the TIC and TSC (like the blob does) instead of the CB upload mechanism, we can remove the 2D.0100 flush without getting the issue that wrong (i.e. probably those set earlier) textures are used. Looks like this might the better way, even though attempts to do the same in the DDX failed. This can provide a good speed boost in some cases, too. I'll wait a while

On Tue, 14 Feb 2017, Vitaly Kuznetsov wrote: > Hi, > > while we're still waiting for a definitive ACK from Microsoft that the > algorithm is good for SMP case (as we can't prevent the code in vdso from > migrating between CPUs) I'd like to send v2 with some modifications to keep > the discussion going. Migration is irrelevant. The TSC page is guest global so

On Wed, 15 Feb 2017, Vitaly Kuznetsov wrote: > Actually, we already have an implementation of TSC page update in KVM > (see arch/x86/kvm/hyperv.c, kvm_hv_setup_tsc_page()) and the update does > the following: > > 0) stash seq into seq_prev > 1) seq = 0 making all reads from the page invalid > 2) smp_wmb() > 3) update tsc_scale, tsc_offset > 4) smp_wmb() > 5) set seq

I've pushed this change already actually. No one seems to know if this option is safe. If you see strange timing-related things happening in libguestfs, let us know! Rich.

> On Dec 17, 2015, at 11:58 PM, Earl A Ramirez <earlaramirez at gmail.com> wrote: > I get > the following error: > > [ 0.000000] tsc: Fast TSC calibration failed TSC is a high accuracy CPU clock. TSC can fail due to motherboard hardware fault on multi processor servers. But the kernel usually fails back to the less accurate default hpet clock. Do other versions/kernels work

Migrate the last TSC values for more accurate timekeeping during live migration Signed-off-by: Dave Winchell <dwinchell@virtualiron.com> Signed-off-by: Ben Guthro <bguthro@virtualiron.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Dear All, I have downloaded CentOS 7.2.1511 DVD and tried to install it on a new laptop that comes with an Intel i7 6th generation processor and don't matter which option I use (install, test media or troubleshooting); I get the following error: [ 0.000000] tsc: Fast TSC calibration failed [ 0.321345] pnp 00:0d: can't evaluate _CRS: 1 At this time I am not able to use any keys on the

Hi all. I just upgraded my server from 4.7-Stable to 5.0-Release by a full install. Now I hit a problem with the date.. the time goes much faster than normal.. maybe twice as normal... this morning I found the following kernel log in /var/log/messages May 26 17:23:58 jupiter kernel: Timecounter "i8254" frequency 1193182 Hz May 26 17:23:58 jupiter kernel: Timecounter "TSC"

As a preparation to making Hyper-V TSC page suitable for vDSO move the TSC page reading logic to asm/mshyperv.h. While on it, do the following - Document the reading algorithm. - Simplify the code a bit. - Add explicit READ_ONCE() to not rely on 'volatile'. - Add explicit barriers to prevent re-ordering (we need to read sequence strictly before and after) - Use mul_u64_u64_shr() instead

Thomas Gleixner <tglx at linutronix.de> writes: > On Wed, 15 Feb 2017, Vitaly Kuznetsov wrote: >> Actually, we already have an implementation of TSC page update in KVM >> (see arch/x86/kvm/hyperv.c, kvm_hv_setup_tsc_page()) and the update does >> the following: >> >> 0) stash seq into seq_prev >> 1) seq = 0 making all reads from the page invalid