Displaying 2 results from an estimated 2 matches for "xc_cpufeature".
2011 Nov 24
0
[PATCH 4/6] X86: Disable PCID/INVPCID for pv
X86: Disable PCID/INVPCID for pv
This patch disable PCID/INVPCID for pv.
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
diff -r 0b15aa9541dc tools/libxc/xc_cpufeature.h
--- a/tools/libxc/xc_cpufeature.h Thu Nov 17 18:41:59 2011 +0800
+++ b/tools/libxc/xc_cpufeature.h Thu Nov 17 23:09:45 2011 +0800
@@ -78,6 +78,7 @@
#define X86_FEATURE_CX16 13 /* CMPXCHG16B */
#define X86_FEATURE_XTPR 14 /* Send Task Priority Messages */
#define X86_FEATURE_PDCM...
2012 Sep 20
0
[PATCH 3/3] Expose tsc adjust to hvm guest
Expose tsc adjust to hvm guest
Intel latest SDM (17.13.3) release a new MSR
CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported.
This patch expose it to hvm guest.
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
diff -r a6d12a1bc758 tools/libxc/xc_cpufeature.h
--- a/tools/libxc/xc_cpufeature.h Thu Sep 20 00:03:25 2012 +0800
+++ b/tools/libxc/xc_cpufeature.h Thu Sep 20 21:50:55 2012 +0800
@@ -128,6 +128,7 @@
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
#define X86_FEATURE_FSGSBASE 0 /* {RD,WR}{FS,GS}BASE instructions */
+#def...