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Samuel Pitoiset

2016-Oct-27 17:19 UTC

[Nouveau] [PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation

Are you sure this refactoring doesn't break anything?

Few comments inline.

On 10/27/2016 04:02 PM, Ilia Mirkin wrote:> This flips GM10x to using the updated format, which is what I tested
> with. However GM20x and GP10x also use this TIC format.
>
> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
> ---
>  src/nvc0_accel.c | 11 ++++++++++
>  src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
>  src/nvc0_exa.c   | 23 ++++---------------
>  src/nvc0_xv.c    | 67
+++++++++++++++++++-------------------------------------
>  4 files changed, 93 insertions(+), 64 deletions(-)
>
> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
> index 0682806..8da5051 100644
> --- a/src/nvc0_accel.c
> +++ b/src/nvc0_accel.c
> @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
>  		PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
>  		PUSH_DATA (push, (bo->offset + MISC_OFFSET));
>  		PUSH_DATA (push, 1);
> +	} else {
> +		/* Use new TIC format. Not strictly necessary for GM20x+ */
> +		IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
> +		if (pNv->dev->chipset >= 0x120) {
> +			/* Use center sample locations. */
> +			BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
> +			PUSH_DATA (push, 0x88888888);
> +			PUSH_DATA (push, 0x88888888);
> +			PUSH_DATA (push, 0x88888888);
> +			PUSH_DATA (push, 0x88888888);
> +		}
>  	}
>
>  	BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
> diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h
> index 607e97b..959f67f 100644
> --- a/src/nvc0_accel.h
> +++ b/src/nvc0_accel.h
> @@ -7,6 +7,7 @@
>  #include "hwdefs/nvc0_m2mf.xml.h"
>  #include "hwdefs/nv50_defs.xml.h"
>  #include "hwdefs/nv50_texture.h"
> +#include "hwdefs/gm107_texture.xml.h"
>  #include "hwdefs/nv_3ddefs.xml.h"
>
>  /* subchannel assignments, compatible with kepler's fixed layout  */
> @@ -108,4 +109,59 @@ PUSH_DATAu(struct nouveau_pushbuf *push, struct
nouveau_bo *bo,
>  	}
>  }
>
> +static __inline__ void
> +PUSH_TIC(struct nouveau_pushbuf *push, struct nouveau_bo *bo, unsigned
offset,
> +	 unsigned width, unsigned height, unsigned pitch, unsigned format)
> +{
> +	if (push->client->device->chipset < 0x110) {
> +		unsigned tic2 = 0xd0001000;
> +		if (pitch == 0)
> +			tic2 |= 0x00004000;
> +		else
> +			tic2 |= 0x0005c000;
> +		PUSH_DATA(push, format);
> +		PUSH_DATA(push, bo->offset + offset);
> +		PUSH_DATA(push, ((bo->offset + offset) >> 32) |
> +			        (bo->config.nvc0.tile_mode << 18) |
> +			        tic2);
> +		PUSH_DATA(push, 0x00300000);
> +		PUSH_DATA(push, 0x80000000 | width);
> +		PUSH_DATA(push, 0x00010000 | height);
> +		PUSH_DATA(push, 0x03000000);
> +		PUSH_DATA(push, 0x00000000);
> +	} else {
> +		unsigned tile_mode = bo->config.nvc0.tile_mode;
> +		PUSH_DATA(push, (format & 0x3f) | ((format & ~0x3f) <<
1));
> +		PUSH_DATA(push, bo->offset + offset);
> +		if (pitch == 0) {
> +			PUSH_DATA(push, ((bo->offset + offset) >> 32) |
> +				  GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR);
> +			PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
> +				  ((tile_mode & 0x007)) |
> +				  ((tile_mode & 0x070) >> (4 - 3)) |
> +				  ((tile_mode & 0x700) >> (8 - 6)));
> +			PUSH_DATA(push, GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V |
> +				  GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
> +				  GM107_TIC2_4_TEXTURE_TYPE_TWO_D |
> +				  (width - 1));
> +			PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS |
> +				        ((height - 1) & 0xffff));
> +			PUSH_DATA(push, GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO |
> +				        GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE);
> +			PUSH_DATA(push, 0x00000000);
> +		} else {
> +			PUSH_DATA(push, ((bo->offset + offset) >> 32) |
> +				        GM107_TIC2_2_HEADER_VERSION_PITCH);
> +			PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
> +				        (pitch >> 5));
> +			PUSH_DATA(push, GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
> +				  GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP |
> +				  (width - 1));
> +			PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS | (height - 1));
> +			PUSH_DATA(push, 0x000000000);
> +			PUSH_DATA(push, 0x000000000);
> +		}
> +	}
> +}
> +
>  #endif
> diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c
> index a53dfe6..017a7da 100644
> --- a/src/nvc0_exa.c
> +++ b/src/nvc0_exa.c
> @@ -532,20 +532,13 @@ NVC0EXACheckTexture(PicturePtr ppict, PicturePtr
pdpict, int op)
>  static Bool
>  NVC0EXAPictSolid(NVPtr pNv, PicturePtr ppict, unsigned unit)
>  {
> -	uint64_t offset = pNv->scratch->offset + SOLID(unit);
>  	struct nouveau_pushbuf *push = pNv->pushbuf;
>
>  	PUSH_DATAu(push, pNv->scratch, SOLID(unit), 1);
>  	PUSH_DATA (push, ppict->pSourcePict->solidFill.color);
>  	PUSH_DATAu(push, pNv->scratch, TIC_OFFSET + (unit * 32), 8);
> -	PUSH_DATA (push, _(B_C0, G_C1, R_C2, A_C3, 8_8_8_8));
> -	PUSH_DATA (push,  offset);
> -	PUSH_DATA (push, (offset >> 32) | 0xd005d000);
> -	PUSH_DATA (push, 0x00300000);
> -	PUSH_DATA (push, 0x00000001);
You always set bit-31 in PUSH_TIC, but it's not set here, is that intended?
> -	PUSH_DATA (push, 0x00010001);
> -	PUSH_DATA (push, 0x03000000);
> -	PUSH_DATA (push, 0x00000000);
> +	PUSH_TIC  (push, pNv->scratch, SOLID(unit), 1, 1, 4,
> +		   _(B_C0, G_C1, R_C2, A_C3, 8_8_8_8));
>  	PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8);
>  	PUSH_DATA (push, NV50TSC_1_0_WRAPS_REPEAT |
>  			 NV50TSC_1_0_WRAPT_REPEAT |
> @@ -651,16 +644,8 @@ NVC0EXAPictTexture(NVPtr pNv, PixmapPtr ppix,
PicturePtr ppict, unsigned unit)
>
>  	PUSH_REFN (push, bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
>  	PUSH_DATAu(push, pNv->scratch, TIC_OFFSET + (unit * 32), 8);
> -	PUSH_DATA (push, format);
> -	PUSH_DATA (push, bo->offset);
> -	PUSH_DATA (push, (bo->offset >> 32) |
> -			 (bo->config.nvc0.tile_mode << 18) |
> -			 0xd0005000);
> -	PUSH_DATA (push, 0x00300000);
> -	PUSH_DATA (push, (1 << 31) | ppix->drawable.width);
> -	PUSH_DATA (push, (1 << 16) | ppix->drawable.height);
> -	PUSH_DATA (push, 0x03000000);
> -	PUSH_DATA (push, 0x00000000);
> +	PUSH_TIC  (push, bo, 0, ppix->drawable.width,
ppix->drawable.height, 0,
> +		   format);
>
>  	PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8);
>  	if (ppict->repeat) {
> diff --git a/src/nvc0_xv.c b/src/nvc0_xv.c
> index 129c505..c3e58da 100644
> --- a/src/nvc0_xv.c
> +++ b/src/nvc0_xv.c
> @@ -74,7 +74,6 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
>  		{ dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR },
>  	};
>  	struct nouveau_pushbuf *push = pNv->pushbuf;
> -	uint32_t mode = 0xd0005000 | (src->config.nvc0.tile_mode << 18);
>  	float X1, X2, Y1, Y2;
>  	BoxPtr pbox;
>  	int nbox;
> @@ -105,71 +104,49 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
>
>  	PUSH_DATAu(push, pNv->scratch, TIC_OFFSET, 16);
>  	if (id == FOURCC_YV12 || id == FOURCC_I420) {
> -	PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
> +		PUSH_TIC(push, src, packed_y, width, height, 0,
> +			 NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
>  			 NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
>  			 NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
>  			 NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
>  			 NV50TIC_0_0_FMT_8);
> -	PUSH_DATA (push, ((src->offset + packed_y)));
> -	PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode);
> -	PUSH_DATA (push, 0x00300000);
> -	PUSH_DATA (push, width);
Same here, I bet bit-31 is not set. :-)
> -	PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
> -	PUSH_DATA (push, 0x03000000);
> -	PUSH_DATA (push, 0x00000000);
> -	PUSH_DATA (push, NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
> +		PUSH_TIC(push, src, uv, width >> 1, height >> 1, 0,
> +			 NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
>  			 NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
>  			 NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
>  			 NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
>  			 NV50TIC_0_0_FMT_8_8);
> -	PUSH_DATA (push, ((src->offset + uv)));
> -	PUSH_DATA (push, ((src->offset + uv) >> 32) | mode);
> -	PUSH_DATA (push, 0x00300000);
> -	PUSH_DATA (push, width >> 1);
> -	PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | (height >>
1));
> -	PUSH_DATA (push, 0x03000000);
> -	PUSH_DATA (push, 0x00000000);
>  	} else {
> -	if (id == FOURCC_UYVY) {
> -	PUSH_DATA (push, NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
> +		unsigned format;
> +		if (id == FOURCC_UYVY) {
> +		format = NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
>  			 NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
>  			 NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
>  			 NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
> -			 NV50TIC_0_0_FMT_8_8);
> -	} else {
> -	PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
> +			 NV50TIC_0_0_FMT_8_8;
> +		} else {
> +		format = NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
>  			 NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
>  			 NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
>  			 NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
> -			 NV50TIC_0_0_FMT_8_8);
> -	}
> -	PUSH_DATA (push, ((src->offset + packed_y)));
> -	PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode);
> -	PUSH_DATA (push, 0x00300000);
> -	PUSH_DATA (push, width);
> -	PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
> -	PUSH_DATA (push, 0x03000000);
> -	PUSH_DATA (push, 0x00000000);
> -	if (id == FOURCC_UYVY) {
> -	PUSH_DATA (push, NV50TIC_0_0_MAPA_C2 | NV50TIC_0_0_TYPEA_UNORM |
> +			 NV50TIC_0_0_FMT_8_8;
> +		}
> +		PUSH_TIC(push, src, packed_y, width, height, 0, format);
> +
> +		if (id == FOURCC_UYVY) {
> +		format = NV50TIC_0_0_MAPA_C2 | NV50TIC_0_0_TYPEA_UNORM |
>  			 NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
>  			 NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
>  			 NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
> -			 NV50TIC_0_0_FMT_8_8_8_8);
> -	} else {
> -	PUSH_DATA (push, NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
> +			 NV50TIC_0_0_FMT_8_8_8_8;
> +		} else {
> +		format = NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
>  			 NV50TIC_0_0_MAPB_C1 | NV50TIC_0_0_TYPEB_UNORM |
>  			 NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
>  			 NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
> -			 NV50TIC_0_0_FMT_8_8_8_8);
> -	}
> -	PUSH_DATA (push, ((src->offset + packed_y)));
> -	PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode);
> -	PUSH_DATA (push, 0x00300000);
> -	PUSH_DATA (push, (width >> 1));
> -	PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
> -	PUSH_DATA (push, 0x03000000);
> -	PUSH_DATA (push, 0x00000000);
> +			 NV50TIC_0_0_FMT_8_8_8_8;
> +		}
> +		PUSH_TIC(push, src, packed_y, width >> 1, height, 0, format);
>  	}
>
>  	PUSH_DATAu(push, pNv->scratch, TSC_OFFSET, 16);
>

Ilia Mirkin

2016-Oct-27 17:28 UTC

head link

[Nouveau] [PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation

On Thu, Oct 27, 2016 at 1:19 PM, Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:> Are you sure this refactoring doesn't break anything?
>
> Few comments inline.
>
>
> On 10/27/2016 04:02 PM, Ilia Mirkin wrote:
>>
>> This flips GM10x to using the updated format, which is what I tested
>> with. However GM20x and GP10x also use this TIC format.
>>
>> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
>> ---
>>  src/nvc0_accel.c | 11 ++++++++++
>>  src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
>>  src/nvc0_exa.c   | 23 ++++---------------
>>  src/nvc0_xv.c    | 67
>> +++++++++++++++++++-------------------------------------
>>  4 files changed, 93 insertions(+), 64 deletions(-)
>>
>> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
>> index 0682806..8da5051 100644
>> --- a/src/nvc0_accel.c
>> +++ b/src/nvc0_accel.c
>> @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
>>                 PUSH_DATA (push, (bo->offset + MISC_OFFSET) >>
32);
>>                 PUSH_DATA (push, (bo->offset + MISC_OFFSET));
>>                 PUSH_DATA (push, 1);
>> +       } else {
>> +               /* Use new TIC format. Not strictly necessary for
GM20x+
>> */
>> +               IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
>> +               if (pNv->dev->chipset >= 0x120) {
>> +                       /* Use center sample locations. */
>> +                       BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
>> +                       PUSH_DATA (push, 0x88888888);
>> +                       PUSH_DATA (push, 0x88888888);
>> +                       PUSH_DATA (push, 0x88888888);
>> +                       PUSH_DATA (push, 0x88888888);
>> +               }
>>         }
>>
>>         BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
>> diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h
>> index 607e97b..959f67f 100644
>> --- a/src/nvc0_accel.h
>> +++ b/src/nvc0_accel.h
>> @@ -7,6 +7,7 @@
>>  #include "hwdefs/nvc0_m2mf.xml.h"
>>  #include "hwdefs/nv50_defs.xml.h"
>>  #include "hwdefs/nv50_texture.h"
>> +#include "hwdefs/gm107_texture.xml.h"
>>  #include "hwdefs/nv_3ddefs.xml.h"
>>
>>  /* subchannel assignments, compatible with kepler's fixed layout 
*/
>> @@ -108,4 +109,59 @@ PUSH_DATAu(struct nouveau_pushbuf *push, struct
>> nouveau_bo *bo,
>>         }
>>  }
>>
>> +static __inline__ void
>> +PUSH_TIC(struct nouveau_pushbuf *push, struct nouveau_bo *bo, unsigned
>> offset,
>> +        unsigned width, unsigned height, unsigned pitch, unsigned
format)
>> +{
>> +       if (push->client->device->chipset < 0x110) {
>> +               unsigned tic2 = 0xd0001000;
>> +               if (pitch == 0)
>> +                       tic2 |= 0x00004000;
>> +               else
>> +                       tic2 |= 0x0005c000;
>> +               PUSH_DATA(push, format);
>> +               PUSH_DATA(push, bo->offset + offset);
>> +               PUSH_DATA(push, ((bo->offset + offset) >> 32)
|
>> +                               (bo->config.nvc0.tile_mode <<
18) |
>> +                               tic2);
>> +               PUSH_DATA(push, 0x00300000);
>> +               PUSH_DATA(push, 0x80000000 | width);
>> +               PUSH_DATA(push, 0x00010000 | height);
>> +               PUSH_DATA(push, 0x03000000);
>> +               PUSH_DATA(push, 0x00000000);
>> +       } else {
>> +               unsigned tile_mode = bo->config.nvc0.tile_mode;
>> +               PUSH_DATA(push, (format & 0x3f) | ((format &
~0x3f) <<
>> 1));
>> +               PUSH_DATA(push, bo->offset + offset);
>> +               if (pitch == 0) {
>> +                       PUSH_DATA(push, ((bo->offset + offset)
>> 32) |
>> +
>> GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR);
>> +                       PUSH_DATA(push,
GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
>> +                                 ((tile_mode & 0x007)) |
>> +                                 ((tile_mode & 0x070) >> (4
- 3)) |
>> +                                 ((tile_mode & 0x700) >> (8
- 6)));
>> +                       PUSH_DATA(push,
>> GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V |
>> +                                
GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
>> +                                 GM107_TIC2_4_TEXTURE_TYPE_TWO_D |
>> +                                 (width - 1));
>> +                       PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS
|
>> +                                       ((height - 1) & 0xffff));
>> +                       PUSH_DATA(push,
>> GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO |
>> +
>> GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE);
>> +                       PUSH_DATA(push, 0x00000000);
>> +               } else {
>> +                       PUSH_DATA(push, ((bo->offset + offset)
>> 32) |
>> +
>> GM107_TIC2_2_HEADER_VERSION_PITCH);
>> +                       PUSH_DATA(push,
GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
>> +                                       (pitch >> 5));
>> +                       PUSH_DATA(push,
>> GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
>> +
>> GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP |
>> +                                 (width - 1));
>> +                       PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS
|
>> (height - 1));
>> +                       PUSH_DATA(push, 0x000000000);
>> +                       PUSH_DATA(push, 0x000000000);
>> +               }
>> +       }
>> +}
>> +
>>  #endif
>> diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c
>> index a53dfe6..017a7da 100644
>> --- a/src/nvc0_exa.c
>> +++ b/src/nvc0_exa.c
>> @@ -532,20 +532,13 @@ NVC0EXACheckTexture(PicturePtr ppict, PicturePtr
>> pdpict, int op)
>>  static Bool
>>  NVC0EXAPictSolid(NVPtr pNv, PicturePtr ppict, unsigned unit)
>>  {
>> -       uint64_t offset = pNv->scratch->offset + SOLID(unit);
>>         struct nouveau_pushbuf *push = pNv->pushbuf;
>>
>>         PUSH_DATAu(push, pNv->scratch, SOLID(unit), 1);
>>         PUSH_DATA (push, ppict->pSourcePict->solidFill.color);
>>         PUSH_DATAu(push, pNv->scratch, TIC_OFFSET + (unit * 32), 8);
>> -       PUSH_DATA (push, _(B_C0, G_C1, R_C2, A_C3, 8_8_8_8));
>> -       PUSH_DATA (push,  offset);
>> -       PUSH_DATA (push, (offset >> 32) | 0xd005d000);
>> -       PUSH_DATA (push, 0x00300000);
>> -       PUSH_DATA (push, 0x00000001);
>
>
> You always set bit-31 in PUSH_TIC, but it's not set here, is that
intended?
Yep, that's fine. That bit 31 controls the meaning of the last TIC
word. (Which is technically only supported on G84+). However in
practice, we don't use any of those features, and setting that bit on
G80 doesn't hurt anything (I'm pretty sure). On G80 (and without that
word set), that last word is some colorkey-related thing. I don't know
exactly... that mode is never used for anything useful.

  -ilia

Samuel Pitoiset

2016-Oct-27 17:32 UTC

head link

[Nouveau] [PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation

On 10/27/2016 07:28 PM, Ilia Mirkin wrote:> On Thu, Oct 27, 2016 at 1:19 PM, Samuel Pitoiset
> <samuel.pitoiset at gmail.com> wrote:
>> Are you sure this refactoring doesn't break anything?
>>
>> Few comments inline.
>>
>>
>> On 10/27/2016 04:02 PM, Ilia Mirkin wrote:
>>>
>>> This flips GM10x to using the updated format, which is what I
tested
>>> with. However GM20x and GP10x also use this TIC format.
>>>
>>> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
>>> ---
>>>  src/nvc0_accel.c | 11 ++++++++++
>>>  src/nvc0_accel.h | 56
++++++++++++++++++++++++++++++++++++++++++++++
>>>  src/nvc0_exa.c   | 23 ++++---------------
>>>  src/nvc0_xv.c    | 67
>>> +++++++++++++++++++-------------------------------------
>>>  4 files changed, 93 insertions(+), 64 deletions(-)
>>>
>>> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
>>> index 0682806..8da5051 100644
>>> --- a/src/nvc0_accel.c
>>> +++ b/src/nvc0_accel.c
>>> @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
>>>                 PUSH_DATA (push, (bo->offset + MISC_OFFSET)
>> 32);
>>>                 PUSH_DATA (push, (bo->offset + MISC_OFFSET));
>>>                 PUSH_DATA (push, 1);
>>> +       } else {
>>> +               /* Use new TIC format. Not strictly necessary for
GM20x+
>>> */
>>> +               IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
>>> +               if (pNv->dev->chipset >= 0x120) {
>>> +                       /* Use center sample locations. */
>>> +                       BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
>>> +                       PUSH_DATA (push, 0x88888888);
>>> +                       PUSH_DATA (push, 0x88888888);
>>> +                       PUSH_DATA (push, 0x88888888);
>>> +                       PUSH_DATA (push, 0x88888888);
>>> +               }
>>>         }
>>>
>>>         BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
>>> diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h
>>> index 607e97b..959f67f 100644
>>> --- a/src/nvc0_accel.h
>>> +++ b/src/nvc0_accel.h
>>> @@ -7,6 +7,7 @@
>>>  #include "hwdefs/nvc0_m2mf.xml.h"
>>>  #include "hwdefs/nv50_defs.xml.h"
>>>  #include "hwdefs/nv50_texture.h"
>>> +#include "hwdefs/gm107_texture.xml.h"
>>>  #include "hwdefs/nv_3ddefs.xml.h"
>>>
>>>  /* subchannel assignments, compatible with kepler's fixed
layout  */
>>> @@ -108,4 +109,59 @@ PUSH_DATAu(struct nouveau_pushbuf *push,
struct
>>> nouveau_bo *bo,
>>>         }
>>>  }
>>>
>>> +static __inline__ void
>>> +PUSH_TIC(struct nouveau_pushbuf *push, struct nouveau_bo *bo,
unsigned
>>> offset,
>>> +        unsigned width, unsigned height, unsigned pitch, unsigned
format)
>>> +{
>>> +       if (push->client->device->chipset < 0x110) {
>>> +               unsigned tic2 = 0xd0001000;
>>> +               if (pitch == 0)
>>> +                       tic2 |= 0x00004000;
>>> +               else
>>> +                       tic2 |= 0x0005c000;
>>> +               PUSH_DATA(push, format);
>>> +               PUSH_DATA(push, bo->offset + offset);
>>> +               PUSH_DATA(push, ((bo->offset + offset) >>
32) |
>>> +                               (bo->config.nvc0.tile_mode
<< 18) |
>>> +                               tic2);
>>> +               PUSH_DATA(push, 0x00300000);
>>> +               PUSH_DATA(push, 0x80000000 | width);
>>> +               PUSH_DATA(push, 0x00010000 | height);
>>> +               PUSH_DATA(push, 0x03000000);
>>> +               PUSH_DATA(push, 0x00000000);
>>> +       } else {
>>> +               unsigned tile_mode = bo->config.nvc0.tile_mode;
>>> +               PUSH_DATA(push, (format & 0x3f) | ((format
& ~0x3f) <<
>>> 1));
>>> +               PUSH_DATA(push, bo->offset + offset);
>>> +               if (pitch == 0) {
>>> +                       PUSH_DATA(push, ((bo->offset + offset)
>> 32) |
>>> +
>>> GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR);
>>> +                       PUSH_DATA(push,
GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
>>> +                                 ((tile_mode & 0x007)) |
>>> +                                 ((tile_mode & 0x070) >>
(4 - 3)) |
>>> +                                 ((tile_mode & 0x700) >>
(8 - 6)));
>>> +                       PUSH_DATA(push,
>>> GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V |
>>> +                                
GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
>>> +                                 GM107_TIC2_4_TEXTURE_TYPE_TWO_D |
>>> +                                 (width - 1));
>>> +                       PUSH_DATA(push,
GM107_TIC2_5_NORMALIZED_COORDS |
>>> +                                       ((height - 1) &
0xffff));
>>> +                       PUSH_DATA(push,
>>> GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO |
>>> +
>>> GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE);
>>> +                       PUSH_DATA(push, 0x00000000);
>>> +               } else {
>>> +                       PUSH_DATA(push, ((bo->offset + offset)
>> 32) |
>>> +
>>> GM107_TIC2_2_HEADER_VERSION_PITCH);
>>> +                       PUSH_DATA(push,
GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
>>> +                                       (pitch >> 5));
>>> +                       PUSH_DATA(push,
>>> GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
>>> +
>>> GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP |
>>> +                                 (width - 1));
>>> +                       PUSH_DATA(push,
GM107_TIC2_5_NORMALIZED_COORDS |
>>> (height - 1));
>>> +                       PUSH_DATA(push, 0x000000000);
>>> +                       PUSH_DATA(push, 0x000000000);
>>> +               }
>>> +       }
>>> +}
>>> +
>>>  #endif
>>> diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c
>>> index a53dfe6..017a7da 100644
>>> --- a/src/nvc0_exa.c
>>> +++ b/src/nvc0_exa.c
>>> @@ -532,20 +532,13 @@ NVC0EXACheckTexture(PicturePtr ppict,
PicturePtr
>>> pdpict, int op)
>>>  static Bool
>>>  NVC0EXAPictSolid(NVPtr pNv, PicturePtr ppict, unsigned unit)
>>>  {
>>> -       uint64_t offset = pNv->scratch->offset + SOLID(unit);
>>>         struct nouveau_pushbuf *push = pNv->pushbuf;
>>>
>>>         PUSH_DATAu(push, pNv->scratch, SOLID(unit), 1);
>>>         PUSH_DATA (push,
ppict->pSourcePict->solidFill.color);
>>>         PUSH_DATAu(push, pNv->scratch, TIC_OFFSET + (unit * 32),
8);
>>> -       PUSH_DATA (push, _(B_C0, G_C1, R_C2, A_C3, 8_8_8_8));
>>> -       PUSH_DATA (push,  offset);
>>> -       PUSH_DATA (push, (offset >> 32) | 0xd005d000);
>>> -       PUSH_DATA (push, 0x00300000);
>>> -       PUSH_DATA (push, 0x00000001);
>>
>>
>> You always set bit-31 in PUSH_TIC, but it's not set here, is that
intended?
>
> Yep, that's fine. That bit 31 controls the meaning of the last TIC
> word. (Which is technically only supported on G84+). However in
> practice, we don't use any of those features, and setting that bit on
> G80 doesn't hurt anything (I'm pretty sure). On G80 (and without
that
> word set), that last word is some colorkey-related thing. I don't know
> exactly... that mode is never used for anything useful.
Okay, hopefully it will work as expected.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
>
>   -ilia
>

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