Displaying 20 results from an estimated 23 matches for "nvc0_accel".
2016 Oct 27
2
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...anything?
Few comments inline.
On 10/27/2016 04:02 PM, Ilia Mirkin wrote:
> This flips GM10x to using the updated format, which is what I tested
> with. However GM20x and GP10x also use this TIC format.
>
> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
> ---
> src/nvc0_accel.c | 11 ++++++++++
> src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
> src/nvc0_exa.c | 23 ++++---------------
> src/nvc0_xv.c | 67 +++++++++++++++++++-------------------------------------
> 4 files changed, 93 insertions(+), 64 deletions(-)
>
> diff -...
2016 Oct 16
0
[PATCH 2/5] nvc0: make use of the new hwdefs for TEX_CB_INDEX
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/nvc0_accel.c | 2 +-
src/nvc0_accel.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 52a17db..0682806 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -313,7 +313,7 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, 0x00000001);...
2016 Oct 27
1
[PATCH v2 6/7] copy: add maxwell/pascal copy engine classes
0xc0b5 is not in rnndb, I guess it should be GP100_COPY, right?
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
On 10/27/2016 04:02 PM, Ilia Mirkin wrote:
> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
> ---
> src/nouveau_copy.c | 2 ++
> src/nvc0_accel.c | 10 +++++++++-
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c
> index c139de6..7118a7a 100644
> --- a/src/nouveau_copy.c
> +++ b/src/nouveau_copy.c
> @@ -42,6 +42,8 @@ nouveau_copy_init(ScreenPtr pScreen)
>...
2016 Oct 17
2
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
Few comments below.
On 10/16/2016 09:14 PM, Ilia Mirkin wrote:
> This flips GM10x to using the updated format, which is what I tested
> with. However GM20x and GP10x also use this TIC format.
>
> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
> ---
> src/nvc0_accel.c | 11 ++++++++++
> src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
> src/nvc0_exa.c | 22 ++++---------------
> src/nvc0_xv.c | 67 +++++++++++++++++++-------------------------------------
> 4 files changed, 93 insertions(+), 63 deletions(-)
>
> diff -...
2016 Oct 27
0
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...On 10/27/2016 04:02 PM, Ilia Mirkin wrote:
>>
>> This flips GM10x to using the updated format, which is what I tested
>> with. However GM20x and GP10x also use this TIC format.
>>
>> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
>> ---
>> src/nvc0_accel.c | 11 ++++++++++
>> src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
>> src/nvc0_exa.c | 23 ++++---------------
>> src/nvc0_xv.c | 67
>> +++++++++++++++++++-------------------------------------
>> 4 files changed, 93 insertions(+), 64 dele...
2016 Oct 16
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
This flips GM10x to using the updated format, which is what I tested
with. However GM20x and GP10x also use this TIC format.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/nvc0_accel.c | 11 ++++++++++
src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
src/nvc0_exa.c | 22 ++++---------------
src/nvc0_xv.c | 67 +++++++++++++++++++-------------------------------------
4 files changed, 93 insertions(+), 63 deletions(-)
diff --git a/src/nvc0_accel.c b/src...
2016 Oct 27
0
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
This flips GM10x to using the updated format, which is what I tested
with. However GM20x and GP10x also use this TIC format.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/nvc0_accel.c | 11 ++++++++++
src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
src/nvc0_exa.c | 23 ++++---------------
src/nvc0_xv.c | 67 +++++++++++++++++++-------------------------------------
4 files changed, 93 insertions(+), 64 deletions(-)
diff --git a/src/nvc0_accel.c b/src...
2016 Oct 17
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...On 10/16/2016 09:14 PM, Ilia Mirkin wrote:
>>
>> This flips GM10x to using the updated format, which is what I tested
>> with. However GM20x and GP10x also use this TIC format.
>>
>> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
>> ---
>> src/nvc0_accel.c | 11 ++++++++++
>> src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
>> src/nvc0_exa.c | 22 ++++---------------
>> src/nvc0_xv.c | 67
>> +++++++++++++++++++-------------------------------------
>> 4 files changed, 93 insertions(+), 63 dele...
2012 Jul 27
1
[PATCH] nvc0: Add and enable vblank support
...BLANK,
&pNv->glx_vblank))
from = X_CONFIG;
diff --git a/src/nv_proto.h b/src/nv_proto.h
index b546ebd..bcf927d 100644
--- a/src/nv_proto.h
+++ b/src/nv_proto.h
@@ -149,6 +149,7 @@ Bool NVAccelInit2D_NV50(ScrnInfoPtr pScrn);
Bool NVAccelInitNV50TCL(ScrnInfoPtr pScrn);
/* in nvc0_accel.c */
+void NVC0SyncToVBlank(PixmapPtr ppix, BoxPtr box);
Bool NVAccelInitM2MF_NVC0(ScrnInfoPtr pScrn);
Bool NVAccelInitCopy_NVC0(ScrnInfoPtr pScrn);
Bool NVAccelInitP2MF_NVE0(ScrnInfoPtr pScrn);
diff --git a/src/nv_type.h b/src/nv_type.h
index e1ea494..272e34f 100644
--- a/src/nv_type.h
+++ b/sr...
2016 Oct 16
0
[PATCH 5/5] recognize and accelerate GM20x
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
Untested. I don't have the hardware.
src/nv_driver.c | 2 ++
src/nvc0_accel.c | 10 +++++++++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/nv_driver.c b/src/nv_driver.c
index fff83f8..61940a8 100644
--- a/src/nv_driver.c
+++ b/src/nv_driver.c
@@ -390,6 +390,7 @@ NVHasKMS(struct pci_device *pci_dev, struct xf86_platform_device *platform_dev)
case 0x...
2016 Oct 17
2
[PATCH 5/5] recognize and accelerate GM20x
...ast a quick test. :-)
Acked-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
On 10/16/2016 09:14 PM, Ilia Mirkin wrote:
> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
> ---
>
> Untested. I don't have the hardware.
>
> src/nv_driver.c | 2 ++
> src/nvc0_accel.c | 10 +++++++++-
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/src/nv_driver.c b/src/nv_driver.c
> index fff83f8..61940a8 100644
> --- a/src/nv_driver.c
> +++ b/src/nv_driver.c
> @@ -390,6 +390,7 @@ NVHasKMS(struct pci_device *pci_dev, struct xf86_platfo...
2016 Oct 27
0
[PATCH v2 6/7] copy: add maxwell/pascal copy engine classes
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/nouveau_copy.c | 2 ++
src/nvc0_accel.c | 10 +++++++++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c
index c139de6..7118a7a 100644
--- a/src/nouveau_copy.c
+++ b/src/nouveau_copy.c
@@ -42,6 +42,8 @@ nouveau_copy_init(ScreenPtr pScreen)
int engine;
Bool (*init)(NVPtr);...
2016 Oct 27
0
[PATCH v2 7/7] recognize and accelerate GM20x
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/nv_driver.c | 2 ++
src/nvc0_accel.c | 10 +++++++++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/nv_driver.c b/src/nv_driver.c
index fff83f8..61940a8 100644
--- a/src/nv_driver.c
+++ b/src/nv_driver.c
@@ -390,6 +390,7 @@ NVHasKMS(struct pci_device *pci_dev, struct xf86_platform_device *platform_dev)
case 0x...
2017 Mar 22
0
[PATCH xf86-video-nouveau] Add Pascal family support, identical to Maxwell
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
Untested.
src/nouveau_copy.c | 2 ++
src/nouveau_exa.c | 1 +
src/nv_accel_common.c | 1 +
src/nv_driver.c | 3 +++
src/nv_type.h | 1 +
src/nvc0_accel.c | 6 ++++++
6 files changed, 14 insertions(+)
diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c
index 7118a7a..7fbcc87 100644
--- a/src/nouveau_copy.c
+++ b/src/nouveau_copy.c
@@ -42,6 +42,7 @@ nouveau_copy_init(ScreenPtr pScreen)
int engine;
Bool (*init)(NVPtr);
} methods[] = {...
2017 Mar 22
0
[PATCH xf86-video-nouveau v2] Add Pascal family support, identical to Maxwell
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
v1 -> v2: add 0x130 as a valid chip type early on in detection
src/nouveau_copy.c | 2 ++
src/nouveau_exa.c | 1 +
src/nv_accel_common.c | 1 +
src/nv_driver.c | 4 ++++
src/nv_type.h | 1 +
src/nvc0_accel.c | 6 ++++++
6 files changed, 15 insertions(+)
diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c
index 7118a7a..7fbcc87 100644
--- a/src/nouveau_copy.c
+++ b/src/nouveau_copy.c
@@ -42,6 +42,7 @@ nouveau_copy_init(ScreenPtr pScreen)
int engine;
Bool (*init)(NVPtr);
} methods[] = {...
2016 Oct 27
11
[PATCH v2 0/7] Add Maxwell support
...| 867 +++++++++++++++++++++++++----------------
src/nouveau_copy.c | 3 +
src/nouveau_exa.c | 2 +-
src/nouveau_local.h | 2 +-
src/nouveau_xv.c | 2 +-
src/nv_accel_common.c | 1 +
src/nv_driver.c | 3 +
src/nvc0_accel.c | 68 +++-
src/nvc0_accel.h | 57 +++
src/nvc0_exa.c | 71 ++--
src/nvc0_xv.c | 115 +++---
src/shader/Makefile | 23 +-
src/shader/exac8nv110.fp | 47 +++
src/shader/exac8nv110.fpc | 38 ++
src/shader/exacan...
2015 Mar 14
1
[PATCH ddx] Add support for VRAM-less devices to the ddx
....c5a2684 100644
--- a/src/nv_type.h
+++ b/src/nv_type.h
@@ -122,6 +122,7 @@ typedef struct _NVRec {
struct nouveau_bo *scratch;
Bool ce_enabled;
+ uint32_t vram_domain;
struct nouveau_object *ce_channel;
struct nouveau_pushbuf *ce_pushbuf;
struct nouveau_object *NvCopy;
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 848ca87..7188230 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -242,7 +242,7 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
if (nouveau_pushbuf_space(push, 512, 0, 0) ||
nouveau_pushbuf_refn (push, &(struct nouveau_pushbuf_refn) {
- pNv->scratch,...
2016 Oct 16
10
[PATCH 1/5] hwdefs: update nvc0_3d, add gm107_texture for new TIC format
These are copied directly from the mesa repository.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++
src/hwdefs/nvc0_3d.xml.h | 867 +++++++++++++++++++++++++----------------
2 files changed, 892 insertions(+), 340 deletions(-)
create mode 100644 src/hwdefs/gm107_texture.xml.h
diff --git
2015 Mar 21
0
[PATCH] use defined method names where available
...t.
src/nv10_exa.c | 8 ++++----
src/nv30_exa.c | 20 ++++++++++----------
src/nv40_exa.c | 8 ++++----
src/nv50_accel.c | 6 +++---
src/nv50_accel.h | 1 +
src/nv50_exa.c | 8 ++++----
src/nv50_xv.c | 2 +-
src/nv_accel_common.c | 6 +++---
src/nvc0_accel.c | 4 ++--
src/nvc0_exa.c | 2 +-
10 files changed, 33 insertions(+), 32 deletions(-)
diff --git a/src/nv10_exa.c b/src/nv10_exa.c
index 78bc739..7daa281 100644
--- a/src/nv10_exa.c
+++ b/src/nv10_exa.c
@@ -697,9 +697,9 @@ NVAccelInitNV10TCL(ScrnInfoPtr pScrn)
PUSH_DATA (push, 0)...
2016 Oct 16
2
[PATCH] exa: add GM10x acceleration support
...rmat to be updated
for that to work. But this is a step in that direction.
src/Makefile.am | 16 ++++++++
src/nouveau_copy.c | 1 +
src/nouveau_exa.c | 2 +-
src/nouveau_xv.c | 2 +-
src/nv_accel_common.c | 1 +
src/nv_driver.c | 1 +
src/nvc0_accel.c | 37 ++++++++++++++---
src/nvc0_exa.c | 48 ++++++++++++++++++++--
src/nvc0_xv.c | 48 ++++++++++++++++++++--
src/shader/Makefile | 23 ++++++++---
src/shader/exac8nv110.fp | 47 +++++++++++++++++++++
src/shader/exac8nv110.fpc | 38 +++++++++++++++++...