Displaying 20 results from an estimated 124 matches for "push_data".
2016 Oct 17
2
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...--------------------
> 4 files changed, 93 insertions(+), 63 deletions(-)
>
> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
> index 0682806..8da5051 100644
> --- a/src/nvc0_accel.c
> +++ b/src/nvc0_accel.c
> @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
> PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
> PUSH_DATA (push, (bo->offset + MISC_OFFSET));
> PUSH_DATA (push, 1);
> + } else {
> + /* Use new TIC format. Not strictly necessary for GM20x+ */
Yes, but it's also enabled by default in mesa, looks fine.
> + IMMED...
2016 Oct 27
2
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...--------------------
> 4 files changed, 93 insertions(+), 64 deletions(-)
>
> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
> index 0682806..8da5051 100644
> --- a/src/nvc0_accel.c
> +++ b/src/nvc0_accel.c
> @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
> PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
> PUSH_DATA (push, (bo->offset + MISC_OFFSET));
> PUSH_DATA (push, 1);
> + } else {
> + /* Use new TIC format. Not strictly necessary for GM20x+ */
> + IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
> + if (pNv->dev->chip...
2016 Oct 16
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...67 +++++++++++++++++++-------------------------------------
4 files changed, 93 insertions(+), 63 deletions(-)
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 0682806..8da5051 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
PUSH_DATA (push, (bo->offset + MISC_OFFSET));
PUSH_DATA (push, 1);
+ } else {
+ /* Use new TIC format. Not strictly necessary for GM20x+ */
+ IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
+ if (pNv->dev->chipset >= 0x120) {
+ /* Use...
2016 Oct 27
0
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...67 +++++++++++++++++++-------------------------------------
4 files changed, 93 insertions(+), 64 deletions(-)
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 0682806..8da5051 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
PUSH_DATA (push, (bo->offset + MISC_OFFSET));
PUSH_DATA (push, 1);
+ } else {
+ /* Use new TIC format. Not strictly necessary for GM20x+ */
+ IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
+ if (pNv->dev->chipset >= 0x120) {
+ /* Use...
2016 Oct 17
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...d, 93 insertions(+), 63 deletions(-)
>>
>> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
>> index 0682806..8da5051 100644
>> --- a/src/nvc0_accel.c
>> +++ b/src/nvc0_accel.c
>> @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
>> PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
>> PUSH_DATA (push, (bo->offset + MISC_OFFSET));
>> PUSH_DATA (push, 1);
>> + } else {
>> + /* Use new TIC format. Not strictly necessary for GM20x+
>> */
>
>...
2015 Mar 21
0
[PATCH] use defined method names where available
...---
src/nvc0_accel.c | 4 ++--
src/nvc0_exa.c | 2 +-
10 files changed, 33 insertions(+), 32 deletions(-)
diff --git a/src/nv10_exa.c b/src/nv10_exa.c
index 78bc739..7daa281 100644
--- a/src/nv10_exa.c
+++ b/src/nv10_exa.c
@@ -697,9 +697,9 @@ NVAccelInitNV10TCL(ScrnInfoPtr pScrn)
PUSH_DATA (push, 0);
}
- BEGIN_NV04(push, SUBC_3D(0x290), 1);
+ BEGIN_NV04(push, NV10_3D(UNK0290), 1);
PUSH_DATA (push, (0x10<<16)|1);
- BEGIN_NV04(push, SUBC_3D(0x3f4), 1);
+ BEGIN_NV04(push, NV10_3D(UNK03F4), 1);
PUSH_DATA (push, 0);
BEGIN_NV04(push, NV04_GRAPH(3D, NOP), 1);
@@ -707,12 +7...
2014 Feb 13
2
[PATCH] nv50: make sure to clear _all_ layers of all attachments
...0_state_validate.c b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
index f953422..100d02d 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
@@ -65,6 +65,7 @@ nv50_validate_fb(struct nv50_context *nv50)
PUSH_DATA (push, sf->height);
BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
PUSH_DATA (push, array_mode | array_size);
+ nv50->rt_array_mode = array_mode | array_size;
} else {
PUSH_DATA (push, 0);
PUSH_DATA (push, 0);
diff --git a/src/gallium/drive...
2016 Oct 27
0
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...d, 93 insertions(+), 64 deletions(-)
>>
>> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
>> index 0682806..8da5051 100644
>> --- a/src/nvc0_accel.c
>> +++ b/src/nvc0_accel.c
>> @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
>> PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
>> PUSH_DATA (push, (bo->offset + MISC_OFFSET));
>> PUSH_DATA (push, 1);
>> + } else {
>> + /* Use new TIC format. Not strictly necessary for GM20x+
>> */
>>...
2014 May 26
2
Implement buffer_clear for nvc0
Hi, please review the following patch!
Thanks,
Tobias Klausmann
2014 May 27
1
[PATCH V3] nvc0: implement clear_buffer
...return;
+ }
+
+ elements = size / data_size;
+
+ height = (elements + 16383) / 16384;
+
+ width = elements / height;
+
+ if (!PUSH_SPACE(push, 40))
+ return;
+
+ PUSH_REFN (push, buf->bo, buf->domain | NOUVEAU_BO_WR);
+
+ BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
+ PUSH_DATAf(push, color.f[0]);
+ PUSH_DATAf(push, color.f[1]);
+ PUSH_DATAf(push, color.f[2]);
+ PUSH_DATAf(push, color.f[3]);
+ BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
+ PUSH_DATA (push, width << 16);
+ PUSH_DATA (push, height << 16);
+
+ IMMED_NVC0(push, NVC0_3D(RT_CONT...
2014 Jan 15
3
[PATCH] nv50, nvc0: don't crash on a null cbuf
...0/nv50_state_validate.c b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
index 86b9a23..7d330c9 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
@@ -20,9 +20,17 @@ nv50_validate_fb(struct nv50_context *nv50)
PUSH_DATA (push, fb->height << 16);
for (i = 0; i < fb->nr_cbufs; ++i) {
- struct nv50_miptree *mt = nv50_miptree(fb->cbufs[i]->texture);
- struct nv50_surface *sf = nv50_surface(fb->cbufs[i]);
- struct nouveau_bo *bo = mt->base.bo;
+ struct nv50_miptree *...
2014 Jun 14
7
[PATCH 0/3] ARB_viewport_array for nvc0
This patch-series implements the ARB_viewport_array for nvc0 and does
a little house-cleanig afterwords.
Tobias Klausmann (3):
nvc0: implement multiple viewports/scissors, enable ARB_viewport_array
nvc0: mark scissor in nvc0_clear_{}
nv50/ir: Remove NV50_SEMANTIC_VIEWPORTINDEX and its last consumer
.../drivers/nouveau/codegen/nv50_ir_driver.h | 1 -
2014 May 26
1
[PATCH V2] nvc0: implement clear_buffer
...elements = size / data_size;
+
+ height = (elements + 16383) / 16384;
+
+ width = elements / height;
+
+ if (!PUSH_SPACE(push, 40))
+ return;
+
+ PUSH_REFN (push, buf->bo, buf->domain | NOUVEAU_BO_WR);
+
+ BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
+ PUSH_DATAf(push, color.f[0]);
+ PUSH_DATAf(push, color.f[1]);
+ PUSH_DATAf(push, color.f[2]);
+ PUSH_DATAf(push, color.f[3]);
+ BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
+ PUSH_DATA (push, width << 16);
+ PUSH_DATA (push, height << 16);
+
+ IMMED_NVC0(...
2014 May 26
0
[PATCH] nvc0: Implement buffer_clear for this type of hardware
...elements = size / data_size;
+
+ height = (elements + 16383) / 16384;
+
+ width = elements / height;
+
+ if (!PUSH_SPACE(push, 40))
+ return;
+
+ PUSH_REFN (push, buf->bo, buf->domain | NOUVEAU_BO_WR);
+
+ BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
+ PUSH_DATAf(push, color.f[0]);
+ PUSH_DATAf(push, color.f[1]);
+ PUSH_DATAf(push, color.f[2]);
+ PUSH_DATAf(push, color.f[3]);
+ BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
+ PUSH_DATA (push, width << 16);
+ PUSH_DATA (push, height << 16);
+
+ BEGIN_NVC0(...
2014 Sep 01
2
[PATCH 1/3] nv50: set the miptree address when clearing bo's in vp2 init
The mt address is about to be used more, make sure it's set
appropriately.
Reported-by: Emil Velikov <emil.l.velikov at gmail.com>
Tested-by: Emil Velikov <emil.l.velikov at gmail.com>
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable at lists.freedesktop.org>
---
src/gallium/drivers/nouveau/nv50/nv84_video.c | 2 ++
1 file
2014 Jan 23
2
[PATCH v2] nv50, nvc0: clear out RT on a null cbuf
...ude "nv50/nv50_context.h"
> -#include "os/os_time.h"
> +#include "nv50/nv50_defs.xml.h"
> +
> +static INLINE void
> +nv50_fb_set_null_rt(struct nouveau_pushbuf *push, unsigned i)
> +{
> + BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(i)), 4);
> + PUSH_DATA (push, 0);
> + PUSH_DATA (push, 0);
> + PUSH_DATA (push, NV50_SURFACE_FORMAT_NONE);
> + PUSH_DATA (push, 0);
> + BEGIN_NV04(push, NV50_3D(RT_HORIZ(i)), 2);
> + PUSH_DATA (push, 64);
> + PUSH_DATA (push, 0);
> +}
>
> static void
> nv50_validate_fb(struct...
2014 May 21
2
[Mesa-dev] [PATCH 02/12] nv50: setup scissors on clear_render_target/depth_stencil
...50_surface.c
> +++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
> @@ -288,6 +288,14 @@ nv50_clear_render_target(struct pipe_context *pipe,
>
> PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
>
> + BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
> + PUSH_DATA (push, ( width << 16) | dstx);
> + PUSH_DATA (push, (height << 16) | dsty);
> + BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
> + PUSH_DATA (push, 8192 << 16);
> + PUSH_DATA (push, 8192 << 16);
> + nv50->scissors_dirty |= 1;
> +
> BEGI...
2018 Feb 04
0
[PATCH 2/2] nv50/xv: add support for depth 30 xv output
...NUM_TEXTURE_PORTS;
adapt->pPortPrivates = (DevUnion*)(&adapt[1]);
diff --git a/src/nv50_xv.c b/src/nv50_xv.c
index b2541b9..ba01c99 100644
--- a/src/nv50_xv.c
+++ b/src/nv50_xv.c
@@ -91,8 +91,9 @@ nv50_xv_image_put(ScrnInfoPtr pScrn,
BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
PUSH_DATA (push, dst->offset >> 32);
PUSH_DATA (push, dst->offset);
- switch (ppix->drawable.bitsPerPixel) {
+ switch (ppix->drawable.depth) {
case 32: PUSH_DATA (push, NV50_SURFACE_FORMAT_BGRA8_UNORM); break;
+ case 30: PUSH_DATA (push, NV50_SURFACE_FORMAT_RGB10_A2_UNORM); break;
cas...
2014 Jan 17
2
[PATCH] nv50, nvc0: only clear out the buffers that we were asked to clear
.../nouveau/nv50/nv50_surface.c b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
index 358f57a..eb27429 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
@@ -408,9 +408,6 @@ nv50_clear(struct pipe_context *pipe, unsigned buffers,
PUSH_DATAf(push, color->f[1]);
PUSH_DATAf(push, color->f[2]);
PUSH_DATAf(push, color->f[3]);
- mode =
- NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G |
- NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A;
}
if (buffers & PIPE_CLEAR_DEPTH) {
@@ -42...
2016 Oct 27
11
[PATCH v2 0/7] Add Maxwell support
I believe I've addressed all the feedback from the first time around, and
also made fixes necessary for GM20x based on testing results. I believe
now it should actually work for all GM10x and GM20x. Further, GP10x should
be very easy to add, but without someone to actually test I didn't want to
claim support for it.
Ilia Mirkin (7):
exa: add GM10x acceleration support
hwdefs: update