Geoff Berry via llvm-dev
2017-Jun-19 18:42 UTC
[llvm-dev] Enabling EarlyCSE w/ MemorySSA by default
Sounds good to me. On 6/19/2017 2:27 PM, Davide Italiano via llvm-dev wrote:> On Mon, Jun 19, 2017 at 11:22 AM, Nemanja Ivanovic via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> For what it's worth, I just ran this on PowerPC and a double bootstrap with >> lit and lnt tests passes everything. >> > I fixed the only bug that has been reported (there were others, but > turned out to be issues in other passes). > Zhendong, did you find anything else? If not, maybe let's wait another > week to give people another chance to test and then decide whether > to flip the switch. > > -- > Davide > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev-- Geoff Berry Employee of Qualcomm Datacenter Technologies, Inc. Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
Geoff Berry via llvm-dev
2017-Jun-27 22:26 UTC
[llvm-dev] Enabling EarlyCSE w/ MemorySSA by default
EarlyCSE w/ MemorySSA has been enabled by default as of r306477 On 6/19/2017 2:42 PM, Geoff Berry via llvm-dev wrote:> Sounds good to me. > > > On 6/19/2017 2:27 PM, Davide Italiano via llvm-dev wrote: >> On Mon, Jun 19, 2017 at 11:22 AM, Nemanja Ivanovic via llvm-dev >> <llvm-dev at lists.llvm.org> wrote: >>> For what it's worth, I just ran this on PowerPC and a double >>> bootstrap with >>> lit and lnt tests passes everything. >>> >> I fixed the only bug that has been reported (there were others, but >> turned out to be issues in other passes). >> Zhendong, did you find anything else? If not, maybe let's wait another >> week to give people another chance to test and then decide whether >> to flip the switch. >> >> -- >> Davide >> _______________________________________________ >> LLVM Developers mailing list >> llvm-dev at lists.llvm.org >> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >-- Geoff Berry Employee of Qualcomm Datacenter Technologies, Inc. Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
Gerolf Hoflehner via llvm-dev
2017-Jun-28 21:40 UTC
[llvm-dev] Enabling EarlyCSE w/ MemorySSA by default
Can you share you compile-time and memory footprint measurements at least for CTMark? For a new pass/feature it would be great to share this with the community before you commit. Or did I miss them? Thanks Gerolf> On Jun 27, 2017, at 3:26 PM, Geoff Berry via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > EarlyCSE w/ MemorySSA has been enabled by default as of r306477 > > > On 6/19/2017 2:42 PM, Geoff Berry via llvm-dev wrote: >> Sounds good to me. >> >> >> On 6/19/2017 2:27 PM, Davide Italiano via llvm-dev wrote: >>> On Mon, Jun 19, 2017 at 11:22 AM, Nemanja Ivanovic via llvm-dev >>> <llvm-dev at lists.llvm.org> wrote: >>>> For what it's worth, I just ran this on PowerPC and a double bootstrap with >>>> lit and lnt tests passes everything. >>>> >>> I fixed the only bug that has been reported (there were others, but >>> turned out to be issues in other passes). >>> Zhendong, did you find anything else? If not, maybe let's wait another >>> week to give people another chance to test and then decide whether >>> to flip the switch. >>> >>> -- >>> Davide >>> _______________________________________________ >>> LLVM Developers mailing list >>> llvm-dev at lists.llvm.org >>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >> > > -- > Geoff Berry > Employee of Qualcomm Datacenter Technologies, Inc. > Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
Possibly Parallel Threads
- Enabling EarlyCSE w/ MemorySSA by default
- [RFC] Switching to MemorySSA-backed Dead Store Elimination (aka cross-bb DSE)
- Enabling EarlyCSE w/ MemorySSA by default
- Enabling EarlyCSE w/ MemorySSA by default
- [GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!