llvm dev - Jul 2016 - Understanding failed assert in reg pressure reduction list scheduler

Hi all,

I'm currently investigating a bug which is causing an assert to fail in
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp. See
https://llvm.org/bugs/show_bug.cgi?id=28753 for repro information.

To my knowledge, this problem only occurs with the SystemZ target. I'm
trying to determine whether the issue is the result of an edge case in the
scheduling code itself, or if it's a SystemZ target problem. However,
I'm
unfamiliar with the scheduling code, so I'm not entirely certain what the
correct behaviour is.

My rough understanding of the problem is that, while attempting to pick a
node to schedule, we're running out of candidates (in
ScheduleDAGRRList::PickNodeToScheduleBottomUp). This causes us to try to
copy a node, and in the process, we call getPhysicalRegisterVT. This
function asserts that the MCInstrDesc associated with the node will have
ImplicitDefs, but in our case, it does not.

In short: does this seem to be a problem of missing information in the
MCInstrDesc, or should we not have arrived at that assert in the first
place?

Thanks,

- Elliot
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Could you post the .ll file with the testcase?

-Krzysztof


On 7/29/2016 2:38 PM, Elliot Colp via llvm-dev wrote:
> Hi all,
>
> I'm currently investigating a bug which is causing an assert to fail in
> lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp. See
> https://llvm.org/bugs/show_bug.cgi?id=28753 for repro information.
>
> To my knowledge, this problem only occurs with the SystemZ target. I'm
> trying to determine whether the issue is the result of an edge case in
> the scheduling code itself, or if it's a SystemZ target problem.
> However, I'm unfamiliar with the scheduling code, so I'm not
entirely
> certain what the correct behaviour is.
>
> My rough understanding of the problem is that, while attempting to pick
> a node to schedule, we're running out of candidates (in
> ScheduleDAGRRList::PickNodeToScheduleBottomUp). This causes us to try to
> copy a node, and in the process, we call getPhysicalRegisterVT. This
> function asserts that the MCInstrDesc associated with the node will have
> ImplicitDefs, but in our case, it does not.
>
> In short: does this seem to be a problem of missing information in the
> MCInstrDesc, or should we not have arrived at that assert in the first
> place?
>
> Thanks,
>
> - Elliot
>
>
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
hosted by The Linux Foundation

Sure, I've attached it to the bug report. Direct link is here:
https://llvm.org/bugs/attachment.cgi?id=16840

- Elliot

"llvm-dev" <llvm-dev-bounces at lists.llvm.org> wrote on
2016/07/29 03:46:41
PM:
> From: Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org>
> To: llvm-dev at lists.llvm.org
> Date: 2016/07/29 03:46 PM
> Subject: Re: [llvm-dev] Understanding failed assert in reg pressure
> reduction list scheduler
> Sent by: "llvm-dev" <llvm-dev-bounces at lists.llvm.org>
>
> Could you post the .ll file with the testcase?
>
> -Krzysztof
>
>
> On 7/29/2016 2:38 PM, Elliot Colp via llvm-dev wrote:
> > Hi all,
> >
> > I'm currently investigating a bug which is causing an assert to
fail in
> > lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp. See
> > https://llvm.org/bugs/show_bug.cgi?id=28753 for repro information.
> >
> > To my knowledge, this problem only occurs with the SystemZ target.
I'm
> > trying to determine whether the issue is the result of an edge case in
> > the scheduling code itself, or if it's a SystemZ target problem.
> > However, I'm unfamiliar with the scheduling code, so I'm not
entirely
> > certain what the correct behaviour is.
> >
> > My rough understanding of the problem is that, while attempting to
pick
> > a node to schedule, we're running out of candidates (in
> > ScheduleDAGRRList::PickNodeToScheduleBottomUp). This causes us to try
to
> > copy a node, and in the process, we call getPhysicalRegisterVT. This
> > function asserts that the MCInstrDesc associated with the node will
have
> > ImplicitDefs, but in our case, it does not.
> >
> > In short: does this seem to be a problem of missing information in the
> > MCInstrDesc, or should we not have arrived at that assert in the first
> > place?
> >
> > Thanks,
> >
> > - Elliot
> >
> >
> >
> > _______________________________________________
> > LLVM Developers mailing list
> > llvm-dev at lists.llvm.org
> > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
> >
>
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> hosted by The Linux Foundation
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
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