Displaying 20 results from an estimated 2142 matches for "reduct".
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2010 Jul 20
3
If help
Hi Y'all,
I have some data in a table with 2 columns. There are two values: "Reduction" and "No Reduction. " I am trying to make a new variable change which recode the combinations from column 1 and 2 into a single number. Here is a snippet from the table:
[1,] "NoReduction" "NoReduction"
[2,] "Reduction"...
2017 Jan 31
2
RFC: Generic IR reductions
Hi all,
During the Nov 2016 dev meeting, we had a hackers’ lab session where we discussed some issues about loop idiom recognition, IR representation and cost modelling. I took an action to write up an RFC about introducing reduction intrinsics to LLVM to represent horizontal operations across vectors.
Vector reductions have been discussed in the past before, notably here: http://lists.llvm.org/pipermail/llvm-dev/2015-November/092379.html
This was in the context of recognizing the patterns for matching more complex cases l...
2019 Apr 05
4
[RFC] Changes to llvm.experimental.vector.reduce intrinsics
...changing the intrinsics for
>> llvm.experimental.vector.reduce.fadd and
>> llvm.experimental.vector.reduce.fmul (see options A and B). I also
>> propose renaming the 'accumulator' operand to 'start value' because
>> for fmul this is the start value of the reduction, rather than a
>> value to which the fmul reduction is accumulated into.
>>
>> [Option A] Always using the start value operand in the reduction
>> (https://reviews.llvm.org/D60261)
>>
>> declare float
>> @llvm.experimental.vector.reduce.v2.fadd.f32....
2019 May 16
4
[RFC] Changes to llvm.experimental.vector.reduce intrinsics
Hello again,
I've been meaning to follow up on this thread for the last couple of weeks, my apologies for the delay.
To summarise the feedback on the proposal for vector.reduce.fadd/fmul:
There seems to be consensus to keep the explicit start value to better accommodate chained reductions (as opposed to generating IR that performs the reduction of the first element using extract/fadd/insert pattern). An important use-case for these reductions is to work inside vectorized loops, where chaining happens through the reduction value's PHI node (i.e. the scalar reduction value fro...
2015 Nov 13
2
[RFC] Introducing a vector reduction add instruction.
Hi
When a reduction instruction is vectorized in a loop, it will be
turned into an instruction with vector operands of the same operation
type. This new instruction has a special property that can give us
more flexibility during instruction selection later: this operation is
valid as long as the reduction of all el...
2019 Apr 10
2
[RFC] Changes to llvm.experimental.vector.reduce intrinsics
...>>>> In this RFC I propose changing the intrinsics for llvm.experimental.vector.reduce.fadd and llvm.experimental.vector.reduce.fmul (see options A and B). I also propose renaming the 'accumulator' operand to 'start value' because for fmul this is the start value of the reduction, rather than a value to which the fmul reduction is accumulated into.
> Note that the LLVM-VP proposal also changes the way reductions are handled in IR (https://reviews.llvm.org/D57504). This could be an opportunity to avoid the "v2" suffix issue: LLVM-VP moves the intrinsic to the...
2017 Jan 31
0
RFC: Generic IR reductions
Hi Amara,
We also had some discussions on the SVE side of reductions on the main
SVE thread, but this description is much more detailed than we had
before.
I don't want to discuss specifically about SVE, as the spec is not out
yet, but I think we can cover a lot of ground until very close to SVE
and do the final step when we get there.
On 31 January 2017...
2015 Nov 25
2
[RFC] Introducing a vector reduction add instruction.
...at google.com>
> To: "Cong Hou" <congh at google.com>
> Cc: "Hal Finkel" <hfinkel at anl.gov>, "llvm-dev" <llvm-dev at lists.llvm.org>
> Sent: Wednesday, November 25, 2015 5:17:58 PM
> Subject: Re: [llvm-dev] [RFC] Introducing a vector reduction add instruction.
>
>
> Hal is probably not questioning about the usefulness of reduction
> recognition and a way to represent it, but the clear semantics of
> the flag. You can probably draw some ideas from OMP SIMD reduction
> clause, or intel's SIMD pragma's reducti...
2019 Apr 04
5
[RFC] Changes to llvm.experimental.vector.reduce intrinsics
Hi all,
While working on a patch to improve codegen for fadd reductions on AArch64, I stumbled upon an outstanding issue with the experimental.vector.reduce.fadd/fmul intrinsics where the accumulator argument is ignored when fast-math is set on the intrinsic call. This behaviour is described in the LangRef (https://www.llvm.org/docs/LangRef.html#id1905) and is ment...
2015 Nov 25
2
[RFC] Introducing a vector reduction add instruction.
..., Nov 25, 2015 at 2:32 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> Hi Cong,
>
> After reading the original RFC and this update, I'm still not entirely sure I understand the semantics of the flag you're proposing to add. Does it having something to do with the ordering of the reduction operations?
The flag is only useful for vectorized reduction for now. I'll give
you an example how this flag is used.
Given the following reduction loop:
int a[N];
int s = 0;
for (int i = 0; i < N; ++i)
s += a[i];
After it is vectorized, we have a reduction operation add whose
opera...
2013 Oct 21
5
[LLVMdev] First attempt at recognizing pointer reduction
Hi Nadav, Arnold,
I managed to find some time to work on the pointer reduction, and I got a
patch that can make "canVectorize()" pass.
Basically what I do is to teach AddReductionVar() about pointers, saying
they don't really have an exit instructions, and that (maybe) the final
store is a good candidate (is it?).
This makes it recognize the writes and read...
2015 Nov 19
5
[RFC] Introducing a vector reduction add instruction.
After some attempt to implement reduce-add in LLVM, I found out a
easier way to detect reduce-add without introducing new IR operations.
The basic idea is annotating phi node instead of add (so that it is
easier to handle other reduction operations). In PHINode class, we can
add a flag indicating if the phi node is a reduction one (the flag can
be set in loop vectorizer for vectorized phi nodes). Then when we
build SDNode for instruction selection, we detect those reduction phi
nodes and then annotate reduction operations. This...
2017 Jan 31
4
RFC: Generic IR reductions
+cc Simon who's also interested in reductions for the any_true,
all_true predicate vectors.
On 31 January 2017 at 20:19, Renato Golin via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> Hi Amara,
>
> We also had some discussions on the SVE side of reductions on the main
> SVE thread, but this description is much more deta...
2013 Oct 21
0
[LLVMdev] First attempt at recognizing pointer reduction
Renato,
can you post a hand-created vectorized IR of how a reduction would work on your example?
I don’t think that recognizing this as a reduction is going to get you far. A reduction is beneficial if the value reduced is only truly needed outside of a loop.
This is not the case here (we are storing/loading from the pointer).
Your example is something like
WR...
2013 Oct 23
2
[LLVMdev] First attempt at recognizing pointer reduction
On 21 October 2013 17:29, Arnold Schwaighofer <aschwaighofer at apple.com>wrote:
> I don’t think that recognizing this as a reduction is going to get you
> far. A reduction is beneficial if the value reduced is only truly needed
> outside of a loop.
> This is not the case here (we are storing/loading from the pointer).
>
Hi Arnold, Nadav,
Let me resurrect this discussion a bit.
There are few things that I need t...
2017 Feb 01
2
RFC: Generic IR reductions
> If you mean "patterns may not be matched, and reduction instructions will not be generated, making the code worse", then this is just a matter of making the patterns obvious and the back-ends robust enough to cope with it, no?
The Back-end should be as robust as possible, I agree. The problem that I see is in adding another kind of complexity to...
2019 Aug 15
4
[LLVM] (RFC) Addition/Support of new Vectorization Pragmas in LLVM
...mpiler, and has supported it since.
This pragma is typically used by application developers who want
vectorized code when the compiler cannot automatically determine safety;
it is not equivalent to the OpenMP SIMD pragma in that the compiler is
still expected to automatically detect such things as reductions.
The Cray implementation accepts an optional 'safevl=<const>' clause,
however this is not commonly used and not really needed for new
implementations.
Characteristics of ivdep:
* ivdep can be applied to any loop in a nest, but only affects the
immediately following loop...
2017 Feb 01
2
RFC: Generic IR reductions
Hi All,
Renato wrote:
>As they say: if it's not broken, don't fix it.
>Let's talk about the reductions that AVX512 and SVE can't handle with IR semantics, but let's not change the current IR semantics for no reason.
Main problem for SVE: We can't write straight-line IR instruction sequence for reduction last value compute, without
knowing #elements in vector to start from.
For non-...
2006 Jul 13
8
can''t convert true into integer
I have a method:
? def reduceProuctInventoryBy(product_id, reduction)
? ? t=Product.find(:first, :conditions =>["id = ?", product_id])
? ? t.qty=(t.qty-reduction)
? ? t.save
? end
and the model:
class Product < ActiveRecord::Base
? validates_presence_of :qty, :specialDescription
? validates_numericality_of :qty
end
but when i run my method, I g...
2013 Oct 23
0
[LLVMdev] First attempt at recognizing pointer reduction
On Oct 23, 2013, at 3:10 PM, Renato Golin <renato.golin at linaro.org> wrote:
> On 23 October 2013 16:05, Arnold Schwaighofer <aschwaighofer at apple.com> wrote:
> In the examples you gave there are no reduction variables in the loop vectorizer’s sense. But, they all have memory accesses that are strided.
>
> This is what I don't get. As far as I understood, a reduction variable is the one that aggregates the computation done by the loop, and is used outside the loop.
>
Yes. But:
for (i...