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Nemanja Ivanovic via llvm-dev

2016-Jul-29 17:57 UTC

[llvm-dev] Help with ISEL matching for an SDAG

I have the following selection DAG:
SelectionDAG has 9 nodes:
  t0: ch = EntryToken
    t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
  t16: i32,ch = load<LD1[%ptr](tbaa=<0x10023c9f448>), anyext from
i8> t0,
t2, undef:i64
    t15: v16i8 = BUILD_VECTOR t16, t16, t16, t16, t16, t16, t16, t16, t16,
t16, t16, t16, t16, t16, t16, t16
  t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t15
  t12: ch = PPCISD::RET_FLAG t11, Register:v16i8 %V2, t11:1

and the following pattern that I'd like to match:

def ScalarLoads {
  dag Li8 =  (i32 (extloadi8 xoaddr:$src));
}

  def : Pat<(v16i8 (build_vector ScalarLoads.Li8, ScalarLoads.Li8,
                                 ScalarLoads.Li8, ScalarLoads.Li8,
                                 ScalarLoads.Li8, ScalarLoads.Li8,
                                 ScalarLoads.Li8, ScalarLoads.Li8,
                                 ScalarLoads.Li8, ScalarLoads.Li8,
                                 ScalarLoads.Li8, ScalarLoads.Li8,
                                 ScalarLoads.Li8, ScalarLoads.Li8,
                                 ScalarLoads.Li8, ScalarLoads.Li8)),
            (v16i8 (VSPLTBs 7, (LXSIBZX xoaddr:$src)))>;

But it doesn't match it. The matching fails at an index that corresponds to
the following line:
OPC_EmitMergeInputChains, 16, 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
14, 15, 16,

I don't know what that line means. Can someone help?
Thanks.
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Krzysztof Parzyszek via llvm-dev

2016-Aug-01 13:17 UTC

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[llvm-dev] Help with ISEL matching for an SDAG

The MergeInputChains operation verifies if the chains that are inputs to 
this node can converge to this point. When it fails, it's usually 
because it would create a cycle in the DAG.

-Krzysztof


On 7/29/2016 12:57 PM, Nemanja Ivanovic via llvm-dev
wrote:> I have the following selection DAG:
> SelectionDAG has 9 nodes:
>   t0: ch = EntryToken
>     t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
>   t16: i32,ch = load<LD1[%ptr](tbaa=<0x10023c9f448>), anyext from
i8>
> t0, t2, undef:i64
>     t15: v16i8 = BUILD_VECTOR t16, t16, t16, t16, t16, t16, t16, t16,
> t16, t16, t16, t16, t16, t16, t16, t16
>   t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t15
>   t12: ch = PPCISD::RET_FLAG t11, Register:v16i8 %V2, t11:1
>
> and the following pattern that I'd like to match:
>
> def ScalarLoads {
>   dag Li8 =  (i32 (extloadi8 xoaddr:$src));
> }
>
>   def : Pat<(v16i8 (build_vector ScalarLoads.Li8, ScalarLoads.Li8,
>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>                                  ScalarLoads.Li8, ScalarLoads.Li8)),
>             (v16i8 (VSPLTBs 7, (LXSIBZX xoaddr:$src)))>;
>
> But it doesn't match it. The matching fails at an index that
corresponds
> to the following line:
> OPC_EmitMergeInputChains, 16, 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
> 14, 15, 16,
>
> I don't know what that line means. Can someone help?
> Thanks.
>
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
hosted by The Linux Foundation

Nemanja Ivanovic via llvm-dev

2016-Aug-01 19:58 UTC

head link

[llvm-dev] Help with ISEL matching for an SDAG

Krzysztof, thank you for your response. However, I don't really understand
how to fix my problem. Namely, I don't understand how this introduces a
cycle in the DAG. Do you have any hints as to what aspect of my TblGen code
is broken?

According to my [rather naive] reading of the Selection DAG just before
ISEL, the BUILD_VECTOR node has 16 inputs (all inputs are the load - t16).
In my pattern, I tried to select exactly that. I would like that node to
select to a pair of instructions (along the lines of):
LXSIBZX 34, 0, 3
VSPLTB 2, 2, 7

If I specify the pattern as:
  def : Pat<(v16i8 (scalar_to_vector ScalarLoads.Li8)),
            (v16i8 (VSPLTBs 7, (LXSIBZX xoaddr:$src)))>;

and convert the BUILD_VECTOR ISD node to a SCALAR_TO_VECTOR followed by a
VECTOR_SHUFFLE, then the match works just fine and the DAG:
SelectionDAG has 11 nodes:
  t0: ch = EntryToken
          t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
        t16: i32,ch = load<LD1[%ptr](tbaa=<0x1003ac5f448>), anyext from
i8>
t0, t2, undef:i64
      t17: v16i8 = scalar_to_vector t16
    t19: v16i8 = vector_shuffle<0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0> t17,
undef:v16i8
  t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t19
  t12: ch = PPCISD::RET_FLAG t11, Register:v16i8 %V2, t11:1

is selected to:
SelectionDAG has 12 nodes:
  t0: ch = EntryToken
      t17: v16i8,ch = VSPLTBs TargetConstant:i32<7>, t23, t23:1
    t19: v16i8 = VSPLTB TargetConstant:i32<15>, t17
  t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t19
    t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
  t23: f64,ch = LXSIBZX<Mem:LD1[%ptr](tbaa=<0x1003ac5f448>)>
Register:i64
%ZERO8, t2, t0
  t12: ch = BLR8 Register:v16i8 %V2, t11, t11:1

As you can see, the pair of instructions I specified actually loads and
splats an i8 value into a vector. So the natural match for that pair is for
a BUILD_VECTOR with a LOAD as input (which doesn't work), rather than for a
SCALAR_TO_VECTOR with a LOAD as input (which does work).
If you have any hints as to what I need to fix, I'd appreciate it because
I'm kind of at my wit's end with this pattern.

On Mon, Aug 1, 2016 at 3:17 PM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> The MergeInputChains operation verifies if the chains that are inputs to
> this node can converge to this point. When it fails, it's usually
because
> it would create a cycle in the DAG.
>
> -Krzysztof
>
>
>
> On 7/29/2016 12:57 PM, Nemanja Ivanovic via llvm-dev wrote:
>
>> I have the following selection DAG:
>> SelectionDAG has 9 nodes:
>>   t0: ch = EntryToken
>>     t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
>>   t16: i32,ch = load<LD1[%ptr](tbaa=<0x10023c9f448>), anyext
from i8>
>> t0, t2, undef:i64
>>     t15: v16i8 = BUILD_VECTOR t16, t16, t16, t16, t16, t16, t16, t16,
>> t16, t16, t16, t16, t16, t16, t16, t16
>>   t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t15
>>   t12: ch = PPCISD::RET_FLAG t11, Register:v16i8 %V2, t11:1
>>
>> and the following pattern that I'd like to match:
>>
>> def ScalarLoads {
>>   dag Li8 =  (i32 (extloadi8 xoaddr:$src));
>> }
>>
>>   def : Pat<(v16i8 (build_vector ScalarLoads.Li8, ScalarLoads.Li8,
>>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>>                                  ScalarLoads.Li8, ScalarLoads.Li8)),
>>             (v16i8 (VSPLTBs 7, (LXSIBZX xoaddr:$src)))>;
>>
>> But it doesn't match it. The matching fails at an index that
corresponds
>> to the following line:
>> OPC_EmitMergeInputChains, 16, 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
13,
>> 14, 15, 16,
>>
>> I don't know what that line means. Can someone help?
>> Thanks.
>>
>>
>> _______________________________________________
>> LLVM Developers mailing list
>> llvm-dev at lists.llvm.org
>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>
>>
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
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