search for: t11

Displaying 20 results from an estimated 53 matches for "t11".

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2016 Jul 29
2
Help with ISEL matching for an SDAG
...has 9 nodes: t0: ch = EntryToken t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t16: i32,ch = load<LD1[%ptr](tbaa=<0x10023c9f448>), anyext from i8> t0, t2, undef:i64 t15: v16i8 = BUILD_VECTOR t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16 t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t15 t12: ch = PPCISD::RET_FLAG t11, Register:v16i8 %V2, t11:1 and the following pattern that I'd like to match: def ScalarLoads { dag Li8 = (i32 (extloadi8 xoaddr:$src)); } def : Pat<(v16i8 (build_vector ScalarLoads.Li8, ScalarLoads.Li8,...
2017 Dec 14
1
change in behavior of c.trellis
> library(latticeExtra) Loading required package: lattice Loading required package: RColorBrewer > t11 <- xyplot(1 ~ 1) > t11 > c(t11, t11) Warning message: In formals(fun) : argument is not a function > version _ platform x86_64-w64-mingw32 arch x86_64 os mingw32 system x86_64, mingw32 status Patched major 3 minor...
2017 Feb 14
2
Ensuring chain dependencies with expansion to libcalls
...emonstrates the problem. t0: ch = EntryToken t2: i64,ch,glue = CopyFromReg t0, Register:i64 %reg0 t4: i64,ch,glue = CopyFromReg t2:1, Register:i64 %reg1, t2:1 t6: i64,ch,glue = CopyFromReg t4:1, Register:i64 %reg2, t4:1 t8: i64,ch,glue = CopyFromReg t6:1, Register:i64 %reg3, t6:1 t11: ch = CopyToReg t0, Register:i64 %vreg0, t2 t13: ch = CopyToReg t0, Register:i64 %vreg1, t4 t15: ch = CopyToReg t0, Register:i64 %vreg2, t8 t26: ch = TokenFactor t11, t13, t15, t2:1, t4:1, t6:1, t8:1 t16: i64 = sdiv t2, t4 Before legalization, there is a single sdiv nod...
2017 Sep 14
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...and the SelectionDAG before TypeLegalizer is like this. t0: ch = EntryToken t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0 t3: ch = ValueType:i32 t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1 t7: i32 = AssertZext t5, ValueType:ch:i1 t8: v2i32 = BUILD_VECTOR t2, t7 t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2 t22: i32 = add t15, Constant:i32<1> t24: ch = CopyToReg t0, Register:i32 %vreg3, t22 t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32...
2007 Mar 01
2
[LLVMdev] Version 1.9 SSA form question
...t3 = shr uint %param.x, ubyte 1 ; <uint> [#uses=1] %.t4 = or uint %.t3, %param.x ; <uint> [#uses=2] %.t7 = shr uint %.t4, ubyte 2 ; <uint> [#uses=1] %.t8 = or uint %.t7, %.t4 ; <uint> [#uses=2] %.t11 = shr uint %.t8, ubyte 4 ; <uint> [#uses=1] %.t12 = or uint %.t11, %.t8 ; <uint> [#uses=2] %.t15 = shr uint %.t12, ubyte 8 ; <uint> [#uses=1] %.t16 = or uint %.t15, %.t12 ; <uint> [#uses=2] %.t19 = shr u...
2017 Sep 15
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...Legalizer is like this. > > t0: ch = EntryToken > t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0 > t3: ch = ValueType:i32 > t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1 > t7: i32 = AssertZext t5, ValueType:ch:i1 > t8: v2i32 = BUILD_VECTOR t2, t7 > t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23> > t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2 > t22: i32 = add t15, Constant:i32<1> > t24: ch = CopyToReg t0, Register:i32 %vreg3, t22 > t27: ch = CopyToReg t0, Register:i32 %vre...
2019 Jun 26
2
How to handle ISD::STORE when both operands are FrameIndex?
...i32<3>, undef:i32 ISEL: Starting pattern match Initial Opcode index to 4 Morphed node: t14: ch = StoreStackF<Mem:(store 4 into %ir.p45, align 8, addrspace 1)> FrameIndex:i32<2>, TargetFrameIndex:i32<3>, t10 ISEL: Match complete! ... ISEL: Starting selection on root node: t11: i32 = FrameIndex<2> ISEL: Starting pattern match Initial Opcode index to 0 Match failed at index 0 LLVM ERROR: Cannot select: t11: i32 = FrameIndex<2> > Cheers. > > Tim. > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http:/&...
2017 Jul 08
2
Error in v64i32 type in x86 backend
...o. but still my instruction is not selected when i run input file in debug mode; getting following errors; ===== Instruction selection begins: BB#1 'vector.body' Selecting: t9: ch = store<ST256[bitcast ([65 x i32]* @c to <64 x i32>*)](align=16)(tbaa=<0x3817578>)> t8, t7, t11, undef:i64 ISEL: Starting pattern match on root node: t9: ch = store<ST256[bitcast ([65 x i32]* @c to <64 x i32>*)](align=16)(tbaa=<0x3817578>)> t8, t7, t11, undef:i64 Skipped scope entry (due to false predicate) at index 14, continuing at 81 Skipped scope entry (due to fals...
2017 Sep 21
1
VSelect Instruction Error
Hello, I am getting this error. What instruction is required to be implemented? LLVM ERROR: Cannot select: t22: v32i32 = vselect t724, t11, t16 t724: v32i32,ch = load<LD128[FixedStack1]> t723, FrameIndex:i64<1>, undef:i64 t659: i64 = FrameIndex<1> t10: i64 = undef t11: v32i32,ch = load<LD128[%sunkaddr45](align=4)(tbaa=<0x481f1e8>)> t0, t8, undef:i64 t8: i64 = add t7, Constant:i64<4>...
2017 Jul 08
2
Error in v64i32 type in x86 backend
...tting following errors; >>>> >>>> >>>> ===== Instruction selection begins: BB#1 'vector.body' >>>> Selecting: t9: ch = store<ST256[bitcast ([65 x i32]* @c to <64 x >>>> i32>*)](align=16)(tbaa=<0x3817578>)> t8, t7, t11, undef:i64 >>>> >>>> ISEL: Starting pattern match on root node: t9: ch = store<ST256[bitcast >>>> ([65 x i32]* @c to <64 x i32>*)](align=16)(tbaa=<0x3817578>)> t8, t7, >>>> t11, undef:i64 >>>> >>>> Skipped s...
2017 Sep 17
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...nd the SelectionDAG before TypeLegalizer is like this. t0: ch = EntryToken t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0 t3: ch = ValueType:i32 t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1 t7: i32 = AssertZext t5, ValueType:ch:i1 t8: v2i32 = BUILD_VECTOR t2, t7 t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2 t22: i32 = add t15, Constant:i32<1> t24: ch = CopyToReg t0, Register:i32 %vreg3, t22 t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32...
2017 Jul 08
5
Error in v64i32 type in x86 backend
...Instruction selection begins: BB#1 'vector.body' >>>>>>>>>>>>>> Selecting: t9: ch = store<ST256[bitcast ([65 x i32]* @c to >>>>>>>>>>>>>> <64 x i32>*)](align=16)(tbaa=<0x3817578>)> t8, t7, t11, >>>>>>>>>>>>>> undef:i64 >>>>>>>>>>>>>> >>>>>>>>>>>>>> ISEL: Starting pattern match on root node: t9: ch = >>>>>>>>>>>>>> store&lt...
2018 Dec 18
2
In ISel, where Constant<0> comes from?
...nitial selection DAG: %bb.0 'main:entry' SelectionDAG has 18 nodes: t0: ch = EntryToken t7: i64 = Constant<0> t9: ch = store<(store 4 into %ir.retval)> t0, Constant:i32<0>, FrameIndex:i64<0>, undef:i64 t2: i32,ch = CopyFromReg t0, Register:i32 %0 t11: ch = store<(store 4 into %ir.argc.addr)> t9, t2, FrameIndex:i64<1>, undef:i64 t4: i64,ch = CopyFromReg t0, Register:i64 %1 t13: ch = store<(store 8 into %ir.argv.addr)> t11, t4, FrameIndex:i64<2>, undef:i64 t16: ch,glue = CopyToReg t13, Register:i32 $eax, Constant:...
2017 Sep 18
1
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...nd the SelectionDAG before TypeLegalizer is like this. t0: ch = EntryToken t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0 t3: ch = ValueType:i32 t5: i32,ch = CopyFromReg t2:1, Register:i32 %vreg1 t7: i32 = AssertZext t5, ValueType:ch:i1 t8: v2i32 = BUILD_VECTOR t2, t7 t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2 t22: i32 = add t15, Constant:i32<1> t24: ch = CopyToReg t0, Register:i32 %vreg3, t22 t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32...
2019 Jun 05
2
Strange behaviour of post-legalising optimisations(?)
...ting new node: t5: i16 = add t2, t4 Creating constant: t6: i16 = Constant<0> Creating new node: t7: i16 = undef Creating new node: t8: i8,ch = load<(load 1 from %ir.scevgep1, !tbaa !2)> t0, t5, undef:i16 Creating new node: t10: i16,ch = CopyFromReg t0, Register:i16 %2 Creating new node: t11: i16 = add t10, t4 Creating new node: t12: ch = store<(store 1 into %ir.scevgep, !tbaa !2)> t8:1, t8, t11, undef:i16 Creating constant: t13: i16 = Constant<1> Creating new node: t14: i16 = add nuw nsw t4, Constant:i16<1> Creating new node: t16: ch = CopyToReg t0, Register:i16 %1,...
2016 Jun 28
2
Instruction selection problem with type i64 - mistaken as v8i64?
...tion of the above piece of code: ===== Instruction selection ends: Selected selection DAG: BB#3 'foo:vector.body.preheader' SelectionDAG has 11 nodes: t0: ch = EntryToken t1: i64 = MOV_ri TargetConstant:i64<0> t3: ch = CopyToReg t0, Register:i64 %vreg23, t1 t11: v8i64 = VLOAD_D TargetConstant:i64<0> t6: ch = CopyToReg t0, Register:v8i64 %vreg24, t11 t8: ch = TokenFactor t3, t6 t9: ch = JMP BasicBlock:ch<vector.body 0xa61440>, t8 [...] Spilling live registers at end of block. Spilling %vreg31 in %R0 to stack slot #5 Spilling %v...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...7, Constant:i64<-1> t10: i64 = and t2, t9 t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 Combining: t11: i64 = Register %R1 Combining: t10: i64 = and t2, t9 Combining: t9: i64 = xor t7, Constant:i64<-1> ... into: t15: i64 = rotl Constant:i64<-2>, t6 ...to this: Optimized lowered selection DAG: BB#0 'bclr64:entry' SelectionDAG has 13 nodes: t0: ch = EntryToken t2: i64,...
2016 Nov 02
3
rotl: undocumented LLVM instruction?
...7, Constant:i64<-1> t10: i64 = and t2, t9 t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 Combining: t11: i64 = Register %R1 Combining: t10: i64 = and t2, t9 Combining: t9: i64 = xor t7, Constant:i64<-1> ... into: t15: i64 = rotl Constant:i64<-2>, t6 Combining: t10: i64 = and t2, t15 Combining: t15: i64 = rotl Constant:i64<-2>, t6 Combining: t14: i64 = Constant<-2> Combi...
2016 Nov 03
3
rotl: undocumented LLVM instruction?
...eg t0, Register:i64 %R1, t10 >> t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 >> >> >> >> Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 >> >> Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 >> >> Combining: t11: i64 = Register %R1 >> >> Combining: t10: i64 = and t2, t9 >> >> Combining: t9: i64 = xor t7, Constant:i64<-1> >> ... into: t15: i64 = rotl Constant:i64<-2>, t6 >> >> ...to this: >> >> Optimized lowered selection DAG: BB#0 'bclr...
2020 Feb 22
2
COPYs between register classes
Hi, On SystemZ there are a set of "access registers" that can be copied in and out of 32-bit GPRs with special instructions. These instructions can only perform the copy using low 32-bit parts of the 64-bit GPRs. As reported and discussed at https://bugs.llvm.org/show_bug.cgi?id=44254, this is currently broken due to the fact that the default register class for 32-bit