Displaying 20 results from an estimated 59 matches for "t16".
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2016 Jul 29
2
Help with ISEL matching for an SDAG
I have the following selection DAG:
SelectionDAG has 9 nodes:
t0: ch = EntryToken
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
t16: i32,ch = load<LD1[%ptr](tbaa=<0x10023c9f448>), anyext from i8> t0,
t2, undef:i64
t15: v16i8 = BUILD_VECTOR t16, t16, t16, t16, t16, t16, t16, t16, t16,
t16, t16, t16, t16, t16, t16, t16
t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t15
t12: ch = PPCISD::RET_FLAG t11, Registe...
2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
...ector_shuffle<0,0,0,0,0,0,0,0> t6, undef:v8i64
t15: v8i64 = BUILD_VECTOR Constant:i64<0>, Constant:i64<1>,
Constant:i64<2>, Constant:i64<3>, Constant:i64<4>, Constant:i64<5>, Constant:i64<6>,
Constant:i64<7>
t16: v8i64 = add t7, t15
t18: ch = CopyToReg t0, Register:v8i64 %vreg16, t16
t20: i64,ch = CopyFromReg t0, Register:i64 %vreg5
t22: i64 = AssertSext t20, ValueType:ch:i8
t23: v8i64 = insert_vector_elt undef:v8i64, t22,...
2017 Jul 20
3
Issue with DAG legalization of brcond, setcc, xor
...2,ch = CopyFromReg t0, Register:i32 %vreg17
t4: i32 = or t2, Constant:i32<256>
t9: i32 = shl t4, Constant:i32<2>
t10: i32 = add t6, t9
t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79
t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1
t16: ch = llvm.tpu.dma.write.1KB.async t0,
TargetConstant:i32<4602>, t10, t12, t15
t18: i32,ch = CopyFromReg t0, Register:i32 %vreg166
t20: i32 = AssertZext t18, ValueType:ch:i1
t23: i1 = setcc t20, Constant:i32<0>, seteq:ch
t25: i32,ch = Copy...
2017 Jul 21
4
Issue with DAG legalization of brcond, setcc, xor
...t4: i32 = or t2, Constant:i32<256>
>> t9: i32 = shl t4, Constant:i32<2>
>> t10: i32 = add t6, t9
>> t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79
>> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1
>> t16: ch = llvm.tpu.dma.write.1KB.async t0, TargetConstant:i32<4602>, t10, t12, t15
>> t18: i32,ch = CopyFromReg t0, Register:i32 %vreg166
>> t20: i32 = AssertZext t18, ValueType:ch:i1
>> t23: i1 = setcc t20, Constant:i32<0>, seteq:ch
>...
2007 Mar 01
2
[LLVMdev] Version 1.9 SSA form question
...%.t8 = or uint %.t7, %.t4 ; <uint> [#uses=2]
%.t11 = shr uint %.t8, ubyte 4 ; <uint> [#uses=1]
%.t12 = or uint %.t11, %.t8 ; <uint> [#uses=2]
%.t15 = shr uint %.t12, ubyte 8 ; <uint> [#uses=1]
%.t16 = or uint %.t15, %.t12 ; <uint> [#uses=2]
%.t19 = shr uint %.t16, ubyte 16 ; <uint>
[#uses=1]
%.t20 = or uint %.t19, %.t16 ; <uint> [#uses=1]
%.t22 = mul uint %.t20, 116069625 ; <uint>
[#uses=1]...
2018 Dec 18
2
In ISel, where Constant<0> comes from?
...t2: i32,ch = CopyFromReg t0, Register:i32 %0
t11: ch = store<(store 4 into %ir.argc.addr)> t9, t2,
FrameIndex:i64<1>, undef:i64
t4: i64,ch = CopyFromReg t0, Register:i64 %1
t13: ch = store<(store 8 into %ir.argv.addr)> t11, t4,
FrameIndex:i64<2>, undef:i64
t16: ch,glue = CopyToReg t13, Register:i32 $eax, Constant:i32<0>
t17: ch = X86ISD::RET_FLAG t16, TargetConstant:i32<0>, Register:i32 $eax, t16:1
where the t16 line corresponds to what you've seen on SPARC.
Cheers.
Tim.
2017 Sep 14
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...er:i32 %vreg2
t22: i32 = add t15, Constant:i32<1>
t24: ch = CopyToReg t0, Register:i32 %vreg3, t22
t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1>
t31: ch = TokenFactor t24, t27
t13: v2i1 = setcc t8, t11, setne:ch
t16: i1 = extract_vector_elt t13, t15
t17: i32 = extract_vector_elt t8, t15
t18: i32 = extract_vector_elt t11, t15
t19: i1 = setcc t17, t18, setne:ch
t20: i1 = xor t16, t19
...
I have not added any vector register class so 'DAGTypeLegalizer' tries...
2016 Sep 03
4
llc error
...de when compiled
using llc.
compilation command - ../llvm-build/bin/llc -filetype=asm -march=x86-64
-mcpu=core-avx2 ex4.ll
The error message is,
LLVM ERROR: Cannot select: t95: v8f32 = X86ISD::SUBV_BROADCAST t17
t17: v4f32,ch = load<LD16[%scevgep](tbaa=<0x4dbcd98>)> t0, t16, undef:i64
t16: i64 = add t2, Constant:i64<16>
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg5
t1: i64 = Register %vreg5
t15: i64 = Constant<16>
t4: i64 = undef
In function: _ZN10soundtouch12TDStretchSSE13calcCrossCorrEPKfS2_Rd
I dug into the LLVM assembly...
2018 Apr 09
2
A way to opt out of a dag combine?
...]. The combine translates this to building a vector from
elements [0, 0]. The problem seems to be treating extract_subvector with
different constants as instances of the same value.
t14: v2f16 = extract_subvector t2, Constant:i32<2>
t15: f16 = extract_vector_elt t14, Constant:i32<0>
t16: v2f16 = extract_subvector t2, Constant:i32<0>
t17: f16 = extract_vector_elt t16, Constant:i32<0>
t9: v2f16 = BUILD_VECTOR t17, t15
... into: t19: v2f16 = vector_shuffle<0,0> t16, undef:v2f16 // fail
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2017 Sep 15
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...t22: i32 = add t15, Constant:i32<1>
> t24: ch = CopyToReg t0, Register:i32 %vreg3, t22
> t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1>
> t31: ch = TokenFactor t24, t27
> t13: v2i1 = setcc t8, t11, setne:ch
> t16: i1 = extract_vector_elt t13, t15
> t17: i32 = extract_vector_elt t8, t15
> t18: i32 = extract_vector_elt t11, t15
> t19: i1 = setcc t17, t18, setne:ch
> t20: i1 = xor t16, t19
>
> ...
>
> I have not added any vector register class s...
2017 Jul 07
2
Error in v64i32 type in x86 backend
...s:i64<[65 x
> i32]* @c> 0
> t13: i64 = TargetGlobalAddress<[65 x i32]* @c> 0
> t3: i64 = undef
> t4: v64i32,ch = load<LD256[bitcast ([65 x i32]* @b to <64 x
> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t16,
> undef:i64
> t16: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x
> i32]* @b> 0
> t15: i64 = TargetGlobalAddress<[65 x i32]* @b> 0
> t3: i64 = undef
> t12: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]*...
2019 Feb 08
2
Unfolded additions of constants after promotion of @llvm.ctlz.i16 on SystemZ
...@llvm.ctlz.i16(i16 %arg, i1 false)
ret i16 %1
}
,gives this optimized DAG as input to instruction selection:
SelectionDAG has 15 nodes:
t0: ch = EntryToken
t2: i32,ch = CopyFromReg t0, Register:i32 %0
t10: i32 = and t2, Constant:i32<65535>
t16: i64 = zero_extend t10
t17: i64 = ctlz t16
t22: i64 = add t17, Constant:i64<-32>
t20: i32 = truncate t22
t15: i32 = add t20, Constant:i32<-16>
t7: ch,glue = CopyToReg t0, Register:i32 $r2l, t15
t8: ch = SystemZISD::RET_FLAG t7, Register:i32 $r2l, t7...
2017 Jul 07
2
Error in v64i32 type in x86 backend
...balAddress:i64<[65 x i32]* @c> 0
>> t13: i64 = TargetGlobalAddress<[65 x i32]* @c> 0
>> t3: i64 = undef
>> t4: v64i32,ch = load<LD256[bitcast ([65 x i32]* @b to <64 x
>> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t16, undef:i64
>> t16: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]* @b> 0
>> t15: i64 = TargetGlobalAddress<[65 x i32]* @b> 0
>> t3: i64 = undef
>> t12: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]* @a> 0
>>...
2017 Jul 06
2
Error in v64i32 type in x86 backend
...t14: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]* @c> 0
t13: i64 = TargetGlobalAddress<[65 x i32]* @c> 0
t3: i64 = undef
t4: v64i32,ch = load<LD256[bitcast ([65 x i32]* @b to <64 x
i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t16, undef:i64
t16: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]* @b> 0
t15: i64 = TargetGlobalAddress<[65 x i32]* @b> 0
t3: i64 = undef
t12: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]* @a> 0
t11: i64 = TargetGlobalAddress<[65 x i...
2017 Sep 21
1
VSelect Instruction Error
Hello,
I am getting this error. What instruction is required to be implemented?
LLVM ERROR: Cannot select: t22: v32i32 = vselect t724, t11, t16
t724: v32i32,ch = load<LD128[FixedStack1]> t723, FrameIndex:i64<1>,
undef:i64
t659: i64 = FrameIndex<1>
t10: i64 = undef
t11: v32i32,ch = load<LD128[%sunkaddr45](align=4)(tbaa=<0x481f1e8>)> t0,
t8, undef:i64
t8: i64 = add t7, Constant:i64<4>...
2016 Sep 03
2
llc error
..../llvm-build/bin/llc -filetype=asm -march=x86-64
>> -mcpu=core-avx2 ex4.ll
>>
>> The error message is,
>>
>> LLVM ERROR: Cannot select: t95: v8f32 = X86ISD::SUBV_BROADCAST t17
>> t17: v4f32,ch = load<LD16[%scevgep](tbaa=<0x4dbcd98>)> t0, t16,
>> undef:i64
>> t16: i64 = add t2, Constant:i64<16>
>> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg5
>> t1: i64 = Register %vreg5
>> t15: i64 = Constant<16>
>> t4: i64 = undef
>> In function: _ZN10soundtouch12TDSt...
2017 Sep 17
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...er:i32 %vreg2
t22: i32 = add t15, Constant:i32<1>
t24: ch = CopyToReg t0, Register:i32 %vreg3, t22
t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1>
t31: ch = TokenFactor t24, t27
t13: v2i1 = setcc t8, t11, setne:ch
t16: i1 = extract_vector_elt t13, t15
t17: i32 = extract_vector_elt t8, t15
t18: i32 = extract_vector_elt t11, t15
t19: i1 = setcc t17, t18, setne:ch
t20: i1 = xor t16, t19
...
I have not added any vector register class so 'DAGTypeLegalizer' t...
2018 Dec 17
4
In ISel, where Constant<0> comes from?
Hello, LLVM devs.
I'm compiling the following simple IR:
define dso_local i32 @main(i32 %argc, i8** %argv) {
entry:
%retval = alloca i32, align 4
%argc.addr = alloca i32, align 4
%argv.addr = alloca i8**, align 8
store i32 0, i32* %retval, align 4
store i32 %argc, i32* %argc.addr, align 4
store i8** %argv, i8*** %argv.addr, align 8
ret i32 0
}
using `llc -march=sparc
2017 Sep 18
1
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...er:i32 %vreg2
t22: i32 = add t15, Constant:i32<1>
t24: ch = CopyToReg t0, Register:i32 %vreg3, t22
t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1>
t31: ch = TokenFactor t24, t27
t13: v2i1 = setcc t8, t11, setne:ch
t16: i1 = extract_vector_elt t13, t15
t17: i32 = extract_vector_elt t8, t15
t18: i32 = extract_vector_elt t11, t15
t19: i1 = setcc t17, t18, setne:ch
t20: i1 = xor t16, t19
...
I have not added any vector register class so 'DAGTypeLegalizer' t...
2002 May 12
1
tinc version 1.0pre7 hangs
...wn to a simple case that can be repeated at will.
I prepared a series of text files with varying numbers of lines. Each
line is:
!"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdef
ghijklmn
wc t*.txt
15 15 1200 t15.txt
16 16 1280 t16.txt
17 17 1360 t17.txt
18 18 1440 t18.txt
20 20 1600 t20.txt
30 30 2400 t30.txt
40 40 3200 t40.txt
>From a client system:
telnet 192.168.200.254 (the hub)
cat t16.txt (works)
cat t17.txt (fails, hangs)
I set the debug level to...