Displaying 7 results from an estimated 7 matches for "li8".
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2016 Jul 29
2
Help with ISEL matching for an SDAG
...t15: v16i8 = BUILD_VECTOR t16, t16, t16, t16, t16, t16, t16, t16, t16,
t16, t16, t16, t16, t16, t16, t16
t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t15
t12: ch = PPCISD::RET_FLAG t11, Register:v16i8 %V2, t11:1
and the following pattern that I'd like to match:
def ScalarLoads {
dag Li8 = (i32 (extloadi8 xoaddr:$src));
}
def : Pat<(v16i8 (build_vector ScalarLoads.Li8, ScalarLoads.Li8,
ScalarLoads.Li8, ScalarLoads.Li8,
ScalarLoads.Li8, ScalarLoads.Li8,
ScalarLoads.Li8, ScalarLo...
2011 Dec 05
3
[LLVMdev] Dead register (was Re: [llvm-commits] [llvm] r145819)
...instruction, in the following instance (this is from the PPC
backend):
BB#38: derived from LLVM BB %for.end50
Predecessors according to CFG: BB#36
%X3<def> = LD 0, <fi#27>; mem:LD8[FixedStack27]
%X4<def> = RLDICR %X3<kill>, 3, 60
%X5<def> = LI8 <jt#0>[TF=4]
%X5<def> = ADDIS8 %X5<kill>, <jt#0>[TF=8]
%X4<def> = LDX %X4<kill>, %X5<kill>; mem:LD8[JumpTable]
MTCTR8 %X4<kill>, %CTR8<imp-def,dead>
BCTR8 %CTR8<imp-use,kill>, %RM<imp-use>
Successo...
2011 Dec 05
0
[LLVMdev] Dead register (was Re: [llvm-commits] [llvm] r145819)
...nstance (this is from the PPC
> backend):
>
> BB#38: derived from LLVM BB %for.end50
> Predecessors according to CFG: BB#36
> %X3<def> = LD 0, <fi#27>; mem:LD8[FixedStack27]
> %X4<def> = RLDICR %X3<kill>, 3, 60
> %X5<def> = LI8 <jt#0>[TF=4]
> %X5<def> = ADDIS8 %X5<kill>, <jt#0>[TF=8]
> %X4<def> = LDX %X4<kill>, %X5<kill>; mem:LD8[JumpTable]
> MTCTR8 %X4<kill>, %CTR8<imp-def,dead>
> BCTR8 %CTR8<imp-use,kill>, %RM<imp-use&...
2011 Dec 06
2
[LLVMdev] Dead register (was Re: [llvm-commits] [llvm] r145819)
...> backend):
> >
> > BB#38: derived from LLVM BB %for.end50
> > Predecessors according to CFG: BB#36
> > %X3<def> = LD 0, <fi#27>; mem:LD8[FixedStack27]
> > %X4<def> = RLDICR %X3<kill>, 3, 60
> > %X5<def> = LI8 <jt#0>[TF=4]
> > %X5<def> = ADDIS8 %X5<kill>, <jt#0>[TF=8]
> > %X4<def> = LDX %X4<kill>, %X5<kill>; mem:LD8[JumpTable]
> > MTCTR8 %X4<kill>, %CTR8<imp-def,dead>
> > BCTR8 %CTR8<imp-use,kill&...
2017 Oct 13
2
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...%vreg20;
G8RC:%vreg21,%vreg19,%vreg20
472B %vreg5<def> = ADDIStocHA %X2, <ga:@A>;
G8RC_and_G8RC_NOX0:%vreg5
480B %vreg6<def> = LDtocL <ga:@A>, %vreg5, %X2<imp-use>;
mem:LD8[GOT] G8RC_and_G8RC_NOX0:%vreg6,%vreg5
504B %X3<def> = LI8 0
512B STD %vreg4, 0, %vreg6; mem:ST8[getelementptr inbounds
([100 x i64], [100 x i64]* @A, i64 0, i64 0)](tbaa=!4) G8RC:%vreg4
G8RC_and_G8RC_NOX0:%vreg6
520B STD %vreg9, 8, %vreg6; mem:ST8[getelementptr inbounds
([100 x i64], [100 x i64]* @A, i64 0, i64 1)](tbaa=!4) G8RC:%...
2017 Oct 13
3
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...vreg19,%vreg20
>> 472B %vreg5<def> = ADDIStocHA %X2, <ga:@A>; G8RC_and_G8RC_NOX0:%vreg5
>> 480B %vreg6<def> = LDtocL <ga:@A>, %vreg5, %X2<imp-use>; mem:LD8[GOT] G8RC_and_G8RC_NOX0:%vreg6,%vreg5
>> 504B %X3<def> = LI8 0
>> 512B STD %vreg4, 0, %vreg6; mem:ST8[getelementptr inbounds ([100 x i64], [100 x i64]* @A, i64 0, i64 0)](tbaa=!4) G8RC:%vreg4 G8RC_and_G8RC_NOX0:%vreg6
>> 520B STD %vreg9, 8, %vreg6; mem:ST8[getelementptr inbounds ([100 x i64], [100 x i64]* @A, i64 0, i64 1)](...
2008 Jun 30
4
Rebuild of kernel 2.6.9-67.0.20.EL failure
Hello list.
I'm trying to rebuild the 2.6.9.67.0.20.EL kernel, but it fails even without
modifications.
How did I try it?
Created a (non-root) build environment (not a mock )
Installed the kernel.scr.rpm and did a
rpmbuild -ba --target=`uname -m` kernel-2.6.spec 2> prep-err.log | tee
prep-out.log
The build failed at the end:
Processing files: kernel-xenU-devel-2.6.9-67.0.20.EL
Checking