llvm dev - Jul 2015 - [LLVMdev] Declare multiple data type for a register class in tblegen

Hi Matt,

I did call addRegisterClass in TargetLowering for all the possible types in
the register. And for typecasting instructions (i32 to i64), it works. Any
other possiblilities?

On Thu, Jul 2, 2015 at 6:12 PM Matt Arsenault <Matthew.Arsenault at
amd.com>
wrote:
> On 07/02/2015 05:56 PM, Xiaochu Liu wrote:
> > Hi everyone,
> >
> > I tried to declare multiple data type [i64, i32, v2i32] for a 64 bit
> > register class GPR. It works OK but I have one problem that is hard to
> > find.
> >
> > When I tried to map a load instruction of a v2i32 type (LOAD
> > v2i32:$dst) to load GPR, it always generate two LOAD i32 instead of
> > one LOAD v2i32. Any folds understand how this works?
> >
> > Xiaochu
> >
> You probably haven't called addRegisterClass in the TargetLowering
> constructor for the vector type. Without it added there, the type
> legalizer will split the vector load into components
>
> -Matt
>
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On 07/02/2015 06:41 PM, Xiaochu Liu wrote:
> Hi Matt,
>
> I did call addRegisterClass in TargetLowering for all the possible 
> types in the register. And for typecasting instructions (i32 to i64), 
> it works. Any other possiblilities?
Try looking at the output of -debug-only=isel and see where the load is 
getting split up. The load isn't reaching instruction selection for your 
pattern to do anything

Thanks. I'm gonna try tomorrow and let you know.

On Thu, Jul 2, 2015 at 6:51 PM Matt Arsenault <Matthew.Arsenault at
amd.com>
wrote:
> On 07/02/2015 06:41 PM, Xiaochu Liu wrote:
> > Hi Matt,
> >
> > I did call addRegisterClass in TargetLowering for all the possible
> > types in the register. And for typecasting instructions (i32 to i64),
> > it works. Any other possiblilities?
> Try looking at the output of -debug-only=isel and see where the load is
> getting split up. The load isn't reaching instruction selection for
your
> pattern to do anything
>
>
>
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