llvm dev - Jul 2015 - [LLVMdev] Declare multiple data type for a register class in tblegen

Thanks. I'm gonna try tomorrow and let you know.

On Thu, Jul 2, 2015 at 6:51 PM Matt Arsenault <Matthew.Arsenault at
amd.com>
wrote:
> On 07/02/2015 06:41 PM, Xiaochu Liu wrote:
> > Hi Matt,
> >
> > I did call addRegisterClass in TargetLowering for all the possible
> > types in the register. And for typecasting instructions (i32 to i64),
> > it works. Any other possiblilities?
> Try looking at the output of -debug-only=isel and see where the load is
> getting split up. The load isn't reaching instruction selection for
your
> pattern to do anything
>
>
>
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Hi Matt,

I tried debug-only=isel and have some more informations.
The steps before 'Legalized selection'( excluding it) all use v2i32
load.
At the step of 'Legalized selection', it replaced one v2i32 load by two
i32
load + shl+ or + bitcast (I have a pattern for convert from v2i32 to
2*i32). In previous steps (initial, lowered, type-legalized), they all use
v2i32 load.
Can you please think of any other places where certain things have to be
declared legal?

Thanks,
Xiaochu


On Fri, Jul 3, 2015 at 12:55 AM Xiaochu Liu <xiaochu1122 at gmail.com>
wrote:
> Thanks. I'm gonna try tomorrow and let you know.
>
> On Thu, Jul 2, 2015 at 6:51 PM Matt Arsenault <Matthew.Arsenault at
amd.com>
> wrote:
>
>> On 07/02/2015 06:41 PM, Xiaochu Liu wrote:
>> > Hi Matt,
>> >
>> > I did call addRegisterClass in TargetLowering for all the possible
>> > types in the register. And for typecasting instructions (i32 to
i64),
>> > it works. Any other possiblilities?
>> Try looking at the output of -debug-only=isel and see where the load is
>> getting split up. The load isn't reaching instruction selection for
your
>> pattern to do anything
>>
>>
>>
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Oh, they have selection details in the end. Let me check that first...

On Sat, Jul 4, 2015 at 4:05 PM Xiaochu Liu <xiaochu1122 at gmail.com>
wrote:
> Hi Matt,
>
> I tried debug-only=isel and have some more informations.
> The steps before 'Legalized selection'( excluding it) all use v2i32
load.
> At the step of 'Legalized selection', it replaced one v2i32 load by
two i32
> load + shl+ or + bitcast (I have a pattern for convert from v2i32 to
> 2*i32). In previous steps (initial, lowered, type-legalized), they all use
> v2i32 load.
> Can you please think of any other places where certain things have to be
> declared legal?
>
> Thanks,
> Xiaochu
>
>
> On Fri, Jul 3, 2015 at 12:55 AM Xiaochu Liu <xiaochu1122 at
gmail.com> wrote:
>
>> Thanks. I'm gonna try tomorrow and let you know.
>>
>> On Thu, Jul 2, 2015 at 6:51 PM Matt Arsenault <Matthew.Arsenault at
amd.com>
>> wrote:
>>
>>> On 07/02/2015 06:41 PM, Xiaochu Liu wrote:
>>> > Hi Matt,
>>> >
>>> > I did call addRegisterClass in TargetLowering for all the
possible
>>> > types in the register. And for typecasting instructions (i32
to i64),
>>> > it works. Any other possiblilities?
>>> Try looking at the output of -debug-only=isel and see where the
load is
>>> getting split up. The load isn't reaching instruction selection
for your
>>> pattern to do anything
>>>
>>>
>>>
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