search for: xiaochu

...> pshufd $212, %xmm4, %xmm4 ## xmm4 = xmm4[0,1,1,3] > > > > Note: > It also vectorizes at SIZE=8. > > Not sure what the exact translation of options from clang-cl to clang is. > Maybe try adding /O3? > > > > > On Fri, Aug 12, 2016 at 11:23 AM, Xiaochu Liu <xiaochu1122 at gmail.com> > wrote: > >> Hi Daniel, >> >> I increased the size of your test to be 128 but -stats still shows no >> loop optimized... >> >> Xiaochu >> >> On Aug 12, 2016 11:11 AM, "Daniel Berlin" <dberlin at...

Oh, they have selection details in the end. Let me check that first... On Sat, Jul 4, 2015 at 4:05 PM Xiaochu Liu <xiaochu1122 at gmail.com> wrote: > Hi Matt, > > I tried debug-only=isel and have some more informations. > The steps before 'Legalized selection'( excluding it) all use v2i32 load. > At the step of 'Legalized selection', it replaced one v2i32 load by two i...

Hi Daniel, I increased the size of your test to be 128 but -stats still shows no loop optimized... Xiaochu On Aug 12, 2016 11:11 AM, "Daniel Berlin" <dberlin at dberlin.org> wrote: > It's not possible to know that A and B don't alias in this example. It's > almost certainly not profitable to add a runtime check given the size of > the loop. > > > try >...

...I also tried clang pragma in my test to force vectorization. What do you think is the problem? Test: #define SIZE 8 void bar(int *A, int* B,int K) { #pragma clang loop vectorize(enable) vectorize_width(2) unroll_count(8) for (int i = 0; i < SIZE; ++i) A[i] += B[i] + K; } Thanks, Xiaochu On Aug 12, 2016 4:06 AM, "Andrey Bokhanko" <andreybokhanko at gmail.com> wrote: > Hi Xiaochu, > > Clang uses -O0 by default, that doesn't run any optimizations. Try > supplying -O1 or higher. > > Yours, > Andrey > > > On Fri, Aug 12, 2016 at 1:04...

...I will try to pass down the mask! I have one more question. In my backend I return CSR_RegMask in getCallPreservedMask and return CSR_SaveList in getCalleeSavedRegs. Is that a correct setup? I dumped the regmask and found that callee saved regs are marked 1 and non-callee saved regs are 0. Thanks, Xiaochu On Wed, Aug 26, 2015 at 5:58 PM Marcello Maggioni <mmaggioni at apple.com> wrote: > Is the preserved mask passed down to your Call instruction in LowerCall ? > > Marcello > > On 26 Aug 2015, at 17:52, Xiaochu Liu via llvm-dev < > llvm-dev at lists.llvm.org> wrote:...

Hi there , I use clang-cl /Qvec test.c to compile the code. But the pass LoopVectorizer is never invoked. I was wondering if this is sufficient to enable auto vectorizer? Thanks, Xiaochu -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160811/8b6cb760/attachment.html>

Hi Hal, Thanks for your reply and it is helpful! I have a quick question: When I use BuildMI to build instructions in this case, do I have to add all three of the register operands explicitly (operand 0 and 1 are the same)? Thanks, Xiaochu On Tue, Nov 24, 2015 at 3:14 PM, Hal Finkel <hfinkel at anl.gov> wrote: > ----- Original Message ----- >> From: "Xiaochu Liu via llvm-dev" <llvm-dev at lists.llvm.org> >> To: "LLVM Developers Mailing List" <llvm-dev at lists.llvm.org> >>...

Thanks. I'm gonna try tomorrow and let you know. On Thu, Jul 2, 2015 at 6:51 PM Matt Arsenault <Matthew.Arsenault at amd.com> wrote: > On 07/02/2015 06:41 PM, Xiaochu Liu wrote: > > Hi Matt, > > > > I did call addRegisterClass in TargetLowering for all the possible > > types in the register. And for typecasting instructions (i32 to i64), > > it works. Any other possiblilities? > Try looking at the output of -debug-only=isel and s...

Nice! Thanks, Tom. It works. On Wed, Sep 9, 2015 at 12:30 PM Tom Stellard <tom at stellard.net> wrote: > On Wed, Sep 09, 2015 at 07:21:30PM +0000, Xiaochu Liu via llvm-dev wrote: > > Dear there, > > > > I'm trying to use clang to invoke my backend to generate obj code using > > command: > > > > clang -target x-linux-gnu global.c -c > > > > Try passing the -fintegrated-as option. > > -Tom >...

...the infrastructure (an outdated one) that I am working on is using gcc+dragonegg to generate llvm code: gcc -m32 -S -c -O0 -fplugin=$(DRAGONEGG_SO) -fplugin-arg-dragonegg-emit-ir $< -o $@.tmp It directly generates llvm code with fadd, etc. I'm not familiar with dragonegg plugin... Thanks, XIaochu On Wed, Mar 16, 2016 at 12:00 PM, Tim Northover <t.p.northover at gmail.com> wrote: > Hi Xiaochu, > > On 16 March 2016 at 11:49, Xiaochu Liu via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> I was trying to compile a code with only integer type variables and &g...

...a code with only integer type variables and integer operations. Clang/llvm kept showing me llvm code with floating-point instructions (fmul, fadd, fptosi, etc.). Is there a way in Clang or llvm to stop the compiler from doing that? My experiment does not allow floating-point operations... Thanks, Xiaochu

...y on CentOS is always so old (Gcc, python). I managed to install local gcc and let cmake know. But I couldn't do so with python. I end up comment out the check in CMakeList.txt which is not good. I was wondering if anyone has experience building llvm (using cmake) using a local python? Thanks, XIaochu -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150722/51e245f0/attachment.html>

...he non-callee-saved registers are still not saved by caller. I want to spill these registers in use on stack right before the call. From my understanding, the register allocator in llvm will do the spill and restoring automatically? Is there anything I was supposed to do to make it happen? Thanks, Xiaochu -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150827/e71882ac/attachment.html>

...list<dag> Pattern> : InstV<(outs GPR:$rd), (ins GPR:$rd, GPR:$rs), !strconcat(OpcodeStr, "\t$rd, $rs"), Pattern> { bits<5> rd; bits<6> rs; let Opcode=Op; } It complains for 'rd'. I was wondering if there is any standard way of doing this? Thanks, Xiaochu

...ta type [i64, i32, v2i32] for a 64 bit register class GPR. It works OK but I have one problem that is hard to find. When I tried to map a load instruction of a v2i32 type (LOAD v2i32:$dst) to load GPR, it always generate two LOAD i32 instead of one LOAD v2i32. Any folds understand how this works? Xiaochu -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150703/bbe463bd/attachment.html>

....c -c But it shows me an error: clang: error: assembler command failed with exit code 1 (use -v to see invocation) I have assembler setup in my backend but it is incorrectly setup (not currently using any assembler). Is there a way for clang to not invoke assembler to generate obj code? Thanks, Xiaochu -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150909/a9ac0f99/attachment.html>

Hi there, In my register allocator, I was trying to get the parent of a register in ARM. That is: D0 <-> S0, S1. Given S0, how am I able to get D0? Thanks, Xiaochu -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160719/3cc73e78/attachment.html>

...%"<bb 4>], [ %l_5.lcssa.i, %"<bb 17>.i" ] It has two identical operands. Are they valid llvm instructions? I am hacking a infrastructure which generates these IR. I was wondering if I should make my tool support this or somehow manage to resolve this situation. Thanks, Xiaochu

...att, I did call addRegisterClass in TargetLowering for all the possible types in the register. And for typecasting instructions (i32 to i64), it works. Any other possiblilities? On Thu, Jul 2, 2015 at 6:12 PM Matt Arsenault <Matthew.Arsenault at amd.com> wrote: > On 07/02/2015 05:56 PM, Xiaochu Liu wrote: > > Hi everyone, > > > > I tried to declare multiple data type [i64, i32, v2i32] for a 64 bit > > register class GPR. It works OK but I have one problem that is hard to > > find. > > > > When I tried to map a load instruction of a v2i32 type (LOA...

yes, this is valid assuming bb9 dominates bb10. Not sure what you mean by "support this", unless your tool doesn't handle certain types of CFG's On Wed, Mar 30, 2016 at 8:12 PM, Xiaochu Liu via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Dear there, > > Is the following phi instruction valid? > > %j_8 = phi i32 [ %j_100, %"<bb 13>" ], [ %j_9133, %"<bb 10>" ], [ > %j_9133, %"<bb 9>" ] > > Variable %j...