Displaying 20 results from an estimated 1000 matches similar to: "[LLVMdev] Declare multiple data type for a register class in tblegen"
2015 Jul 03
2
[LLVMdev] Declare multiple data type for a register class in tblegen
Hi Matt,
I did call addRegisterClass in TargetLowering for all the possible types in
the register. And for typecasting instructions (i32 to i64), it works. Any
other possiblilities?
On Thu, Jul 2, 2015 at 6:12 PM Matt Arsenault <Matthew.Arsenault at amd.com>
wrote:
> On 07/02/2015 05:56 PM, Xiaochu Liu wrote:
> > Hi everyone,
> >
> > I tried to declare multiple data
2015 Jul 04
3
[LLVMdev] Declare multiple data type for a register class in tblegen
Oh, they have selection details in the end. Let me check that first...
On Sat, Jul 4, 2015 at 4:05 PM Xiaochu Liu <xiaochu1122 at gmail.com> wrote:
> Hi Matt,
>
> I tried debug-only=isel and have some more informations.
> The steps before 'Legalized selection'( excluding it) all use v2i32 load.
> At the step of 'Legalized selection', it replaced one v2i32
2015 Jul 03
2
[LLVMdev] Declare multiple data type for a register class in tblegen
Thanks. I'm gonna try tomorrow and let you know.
On Thu, Jul 2, 2015 at 6:51 PM Matt Arsenault <Matthew.Arsenault at amd.com>
wrote:
> On 07/02/2015 06:41 PM, Xiaochu Liu wrote:
> > Hi Matt,
> >
> > I did call addRegisterClass in TargetLowering for all the possible
> > types in the register. And for typecasting instructions (i32 to i64),
> > it works.
2016 Aug 18
3
extract_vector_elt type mismatch?
Hi there,
I'm trying to map extract_vector_elt use the following pattern in tbl file.
Def : Pat <(i64 (extractelt v2i32:$src, 0)), (i64 (SRLIMM GPR:$src, 32))>;
But the tblgen shows :
Type inference contradiction found , forcing v2i32 to have a vector element
of type i64
But the manual says this instruction allows return type to be larger than
element type.
Anyone can show me any
2012 Mar 02
1
[LLVMdev] vector shuffle emulation/expand in backend?
I'm having some troubles implementing vector support to our custom backend
It seems that llvm cannot emulate shuffle with extracts, inserts and builds?
I've enabled vector registers with
addRegisterClass(MVT::v2i32, TCE::V2I32RegsRegisterClass);
addRegisterClass(MVT::v2f32, TCE::V2F32RegsRegisterClass);
and created patterns for most vector instructions, including insert,
extract and
2015 Nov 24
2
[backend]two-address encoding in llvm tblgen
Hi Hal,
Thanks for your reply and it is helpful!
I have a quick question:
When I use BuildMI to build instructions in this case, do I have to
add all three of the register operands explicitly (operand 0 and 1 are
the same)?
Thanks,
Xiaochu
On Tue, Nov 24, 2015 at 3:14 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> ----- Original Message -----
>> From: "Xiaochu Liu via
2015 Apr 03
2
[LLVMdev] How to enable use of 64bit load/store for 32bit architecture
> On Apr 2, 2015, at 2:07 PM, Tom Stellard <tom at stellard.net> wrote:
>
> On Thu, Apr 02, 2015 at 01:35:55PM -0700, Pete Cooper wrote:
>> Hi James, Jim
>>
>> If you *really* want this to work in selection DAG then there is a solution, but its not pretty.
>>
>> First make i64 not be legal. Then, assuming the regclass you gave has some subregs, you
2016 Aug 12
4
Invoke loop vectorizer
I'm not compiling it to x86. Should loop optimizer something independent of
the target? If so, should the vectorized code on IR level?
On Aug 12, 2016 11:39 AM, "Daniel Berlin" <dberlin at dberlin.org> wrote:
> cat > test.c
>
> #define SIZE 128
>
> void bar(int *restrict A, int* restrict B,int K) {
>
> #pragma clang loop vectorize(enable)
2015 Jul 22
3
[LLVMdev] build llvm on CentOS
Hi there,
I was trying to build llvm on CentOS. The problem is that library on CentOS
is always so old (Gcc, python). I managed to install local gcc and let
cmake know. But I couldn't do so with python. I end up comment out the
check in CMakeList.txt which is not good.
I was wondering if anyone has experience building llvm (using cmake) using
a local python?
Thanks,
XIaochu
--------------
2015 Aug 27
2
preserve registers across function call
Hi Marcello,
Thanks for your reply. I will try to pass down the mask!
I have one more question. In my backend I return CSR_RegMask in
getCallPreservedMask and return CSR_SaveList in getCalleeSavedRegs. Is that
a correct setup? I dumped the regmask and found that callee saved regs are
marked 1 and non-callee saved regs are 0.
Thanks,
Xiaochu
On Wed, Aug 26, 2015 at 5:58 PM Marcello Maggioni
2016 Mar 16
2
How to prevent clang/llvm from generating floating-point instructions?
Hi Tim,
Thanks for your message! It turns out that the infrastructure (an
outdated one) that I am working on is using gcc+dragonegg to generate
llvm code:
gcc -m32 -S -c -O0 -fplugin=$(DRAGONEGG_SO)
-fplugin-arg-dragonegg-emit-ir $< -o $@.tmp
It directly generates llvm code with fadd, etc. I'm not familiar with
dragonegg plugin...
Thanks,
XIaochu
On Wed, Mar 16, 2016 at 12:00 PM,
2016 Aug 12
2
Invoke loop vectorizer
Hi Daniel,
I increased the size of your test to be 128 but -stats still shows no loop
optimized...
Xiaochu
On Aug 12, 2016 11:11 AM, "Daniel Berlin" <dberlin at dberlin.org> wrote:
> It's not possible to know that A and B don't alias in this example. It's
> almost certainly not profitable to add a runtime check given the size of
> the loop.
>
>
>
2016 Aug 29
2
GVN / Alias Analysis issue with llvm.masked.scatter/gather intrinsics
Hello everyone,
I think I have found an gvn / alias analysis related bug, but before
opening an issue on the tracker I wanted to see if I am missing something.
I have the following testcase:
define spir_kernel void @test(<2 x i32*> %in1, <2 x i32*> %in2, i32* %out) {
> entry:
> ; Just some temporary storage
> %tmp.0 = alloca i32
> %tmp.1 = alloca i32
> %tmp.i =
2015 Nov 24
2
[backend]two-address encoding in llvm tblgen
Dear there,
I'm developing an instruction layout like:
opcode | rd| ts
and its semantics is:
rd= rd opcode rs
But when I describe it in td file like this:
class R<bits<5> Op, string OpcodeStr, list<dag> Pattern>
: InstV<(outs GPR:$rd), (ins GPR:$rd, GPR:$rs), !strconcat(OpcodeStr,
"\t$rd, $rs"), Pattern> {
bits<5> rd;
bits<6> rs;
let
2016 Aug 29
2
GVN / Alias Analysis issue with llvm.masked.scatter/gather intrinsics
this is definitely a bug in AA.
225 for (auto I = CS2.arg_begin(), E = CS2.arg_end(); I != E; ++I) {
226 const Value *Arg = *I;
227 if (!Arg->getType()->isPointerTy())
-> 228 continue;
229 unsigned CS2ArgIdx = std::distance(CS2.arg_begin(), I);
230 auto CS2ArgLoc = MemoryLocation::getForArgument(CS2,
CS2ArgIdx, TLI);
2016 Aug 29
2
GVN / Alias Analysis issue with llvm.masked.scatter/gather intrinsics
+ a few others.
After following this rabbit hole a bit, there are a lot of mutually
recursive calls, etc, that may or may not do the right thing with vectors
of pointers.
I can fix *this* particular bug with the attached patch.
However, it's mostly papering over stuff. Nothing seems to know what to do
with a memorylocation that is a vector of pointers. They all expect
memorylocation to be a
2016 Aug 29
2
GVN / Alias Analysis issue with llvm.masked.scatter/gather intrinsics
Okay, so then it sounds like, for now, the right fix is to stop marking
masked.gather and masked.scatter with intrarg* options.
On Mon, Aug 29, 2016, 1:26 PM Philip Reames <listmail at philipreames.com>
wrote:
> We might have specification bug here, but we appear to implement what we
> specified. argmemonly is specified as only considering pointer typed
> arguments. It's
2016 Aug 30
2
GVN / Alias Analysis issue with llvm.masked.scatter/gather intrinsics
----- Original Message -----
> From: "Daniel Berlin" <dberlin at dberlin.org>
> To: "Philip Reames" <listmail at philipreames.com>, "Davide Italiano"
> <davide at freebsd.org>, "Chandler Carruth" <chandlerc at gmail.com>
> Cc: "Chris Sakalis" <chrissakalis at gmail.com>, "David Majnemer"
>
2016 Aug 31
2
GVN / Alias Analysis issue with llvm.masked.scatter/gather intrinsics
Thank you for the quick fix, I can no longer reproduce the issue. As far a
releases go, I am guessing that this is going to be in 4.0?
Best,
Chris
On Tue, Aug 30, 2016 at 9:26 PM, Daniel Berlin <dberlin at dberlin.org> wrote:
> Yeah, i just hope it doesn't regress scatter/gather vector code badly.
> But at least it's correct now?
>
>
> On Tue, Aug 30, 2016 at 1:11
2016 Aug 31
2
GVN / Alias Analysis issue with llvm.masked.scatter/gather intrinsics
Great, thank you!
On Wed, Aug 31, 2016 at 2:07 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> ------------------------------
>
> *From: *"Chris Sakalis" <chrissakalis at gmail.com>
> *To: *"Daniel Berlin" <dberlin at dberlin.org>
> *Cc: *"Hal Finkel" <hfinkel at anl.gov>, "David Majnemer" <
> david.majnemer