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Oh, they have selection details in the end. Let me check that first... On Sat, Jul 4, 2015 at 4:05 PM Xiaochu Liu <xiaochu1122 at gmail.com> wrote: > Hi Matt, > > I tried debug-only=isel and have some more informations. > The steps before 'Legalized selection'( excluding it) all use v2i32 load. > At the step of 'Legalized selection', it replaced one v2i32 load by two i32 > load + shl+...

Thanks. I'm gonna try tomorrow and let you know. On Thu, Jul 2, 2015 at 6:51 PM Matt Arsenault <Matthew.Arsenault at amd.com> wrote: > On 07/02/2015 06:41 PM, Xiaochu Liu wrote: > > Hi Matt, > > > > I did call addRegisterClass in TargetLowering for all the possible > > types in the register. And for typecasting instructions (i32 to i64), > > it works.

...0007fff907f25c9 start + 1 Stack dump: 0. Program arguments: ../build/Debug/bin/llc -march bpf -filetype=obj arith.bc Illegal instruction: 4 On Sun, Aug 2, 2015 at 5:57 PM Alexei Starovoitov < alexei.starovoitov at gmail.com> wrote: > On Sun, Aug 2, 2015 at 12:24 AM, Xiaochu Liu <xiaochu1122 at gmail.com> > wrote: > > Dear there, > > > > I wasn't able to generate obj file for bpf using llc: > > > > llc -march bpf -filetype=obj foo.bc > > > > Anyone knows what is the missing part in their backend? I want to make it > > work for m...

Hi there, I was trying to build llvm on CentOS. The problem is that library on CentOS is always so old (Gcc, python). I managed to install local gcc and let cmake know. But I couldn't do so with python. I end up comment out the check in CMakeList.txt which is not good. I was wondering if anyone has experience building llvm (using cmake) using a local python? Thanks, XIaochu --------------

...ufd $212, %xmm4, %xmm4 ## xmm4 = xmm4[0,1,1,3] > > > > Note: > It also vectorizes at SIZE=8. > > Not sure what the exact translation of options from clang-cl to clang is. > Maybe try adding /O3? > > > > > On Fri, Aug 12, 2016 at 11:23 AM, Xiaochu Liu <xiaochu1122 at gmail.com> > wrote: > >> Hi Daniel, >> >> I increased the size of your test to be 128 but -stats still shows no >> loop optimized... >> >> Xiaochu >> >> On Aug 12, 2016 11:11 AM, "Daniel Berlin" <dberlin at dberlin.org> wro...

Dear there, I wasn't able to generate obj file for bpf using llc: llc -march bpf -filetype=obj foo.bc Anyone knows what is the missing part in their backend? I want to make it work for my project. Thanks, Xiaochu -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150802/e0b55467/attachment.html>

Hi Tim, Thanks for your message! It turns out that the infrastructure (an outdated one) that I am working on is using gcc+dragonegg to generate llvm code: gcc -m32 -S -c -O0 -fplugin=$(DRAGONEGG_SO) -fplugin-arg-dragonegg-emit-ir $< -o $@.tmp It directly generates llvm code with fadd, etc. I'm not familiar with dragonegg plugin... Thanks, XIaochu On Wed, Mar 16, 2016 at 12:00 PM,

Hi Marcello, Thanks for your reply. I will try to pass down the mask! I have one more question. In my backend I return CSR_RegMask in getCallPreservedMask and return CSR_SaveList in getCalleeSavedRegs. Is that a correct setup? I dumped the regmask and found that callee saved regs are marked 1 and non-callee saved regs are 0. Thanks, Xiaochu On Wed, Aug 26, 2015 at 5:58 PM Marcello Maggioni

Hi Hal, Thanks for your reply and it is helpful! I have a quick question: When I use BuildMI to build instructions in this case, do I have to add all three of the register operands explicitly (operand 0 and 1 are the same)? Thanks, Xiaochu On Tue, Nov 24, 2015 at 3:14 PM, Hal Finkel <hfinkel at anl.gov> wrote: > ----- Original Message ----- >> From: "Xiaochu Liu via

Hi Daniel, I increased the size of your test to be 128 but -stats still shows no loop optimized... Xiaochu On Aug 12, 2016 11:11 AM, "Daniel Berlin" <dberlin at dberlin.org> wrote: > It's not possible to know that A and B don't alias in this example. It's > almost certainly not profitable to add a runtime check given the size of > the loop. > > >

Hi everyone, I tried to declare multiple data type [i64, i32, v2i32] for a 64 bit register class GPR. It works OK but I have one problem that is hard to find. When I tried to map a load instruction of a v2i32 type (LOAD v2i32:$dst) to load GPR, it always generate two LOAD i32 instead of one LOAD v2i32. Any folds understand how this works? Xiaochu -------------- next part -------------- An HTML

Hi Matt, I did call addRegisterClass in TargetLowering for all the possible types in the register. And for typecasting instructions (i32 to i64), it works. Any other possiblilities? On Thu, Jul 2, 2015 at 6:12 PM Matt Arsenault <Matthew.Arsenault at amd.com> wrote: > On 07/02/2015 05:56 PM, Xiaochu Liu wrote: > > Hi everyone, > > > > I tried to declare multiple data

Hi there, I am doing relocation in my backend by calling my function getAddrNonPic: SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG)const{ SValue Hi=getTarget(N,Ty,DAG, MyBackend::Hi16); SValue Lo=getTarget(N,Ty,DAG, MyBackend::Lo16); return DAG.getNode(ISD::ADD, DL, Ty, DAG.getNode(MyBackend::Hi16, DL, Ty, Hi), DAG.getNode(MyBackend::Lo16, DL, Ty, Ho)); }

Hi there, I have a mem address pattern basically copied from Sparc: def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex],[]> It can match FrameIndex<0> but was unable to match FrameIndex<1>. What is the difference between the two? How to match FrameIndex<1>? Thanks, Xiaochu -------------- next part -------------- An HTML attachment was scrubbed...

I was trying to do a pattern matching for a rd+imm instruction in my own backend. It looks something like: def: Pat<build_vector v2i16:$src1, v2i16:$src2, (OR (SLLI GPR: $src1,16), GPR:$src2>; OR takes two i32 in registers and SLLI takes one i32 in registers and an immediate. But the immediate '16' does not work here and I tried different ways. May I know if any of you have any idea