Liu Xin
2013-Nov-23 03:17 UTC
[LLVMdev] prevents instruction-scheduler from interfereing instruction pair
Amara, first, thank you for answering. but I found expandPsuedo instructions actually happens before post-RA, like the following code showing: your approach is a little hacky, right? : ) // Expand pseudo instructions before second scheduling pass. addPass(&ExpandPostRAPseudosID); printAndVerify("After ExpandPostRAPseudos"); // Run pre-sched2 passes. if (addPreSched2()) printAndVerify("After PreSched2 passes"); // Second pass scheduler. if (getOptLevel() != CodeGenOpt::None) { addPass(&PostRASchedulerID); printAndVerify("After PostRAScheduler"); } secondly, psuedo instruction is kind of compiler internal representation. I wish our instruction pair can disclose to programmer. intrinsics can do that. thanks, --lx On Fri, Nov 22, 2013 at 9:45 PM, Amara Emerson <amara.emerson at arm.com>wrote:> What about describing the instruction pairs as pseudo-instructions, and > then expanding them in a machine function pass at the pre-emit stage? > > > > Amara >-------------- next part -------------- An HTML attachment was scrubbed... URL: <lists.llvm.org/pipermail/llvm-dev/attachments/20131123/88eb3f0f/attachment.html>
Amara Emerson
2013-Nov-23 12:37 UTC
[LLVMdev] prevents instruction-scheduler from interfereing instruction pair
What I meant was to write your own expansion pass and run it after the scheduler passes, e.g. in the pre-emit stage.> if (addPreEmitPass())printAndVerify("After PreEmit passes") Though if it's too hacky for you then fair enough. Amara On 23 November 2013 03:17, Liu Xin <navy.xliu at gmail.com> wrote:> Amara, > > first, thank you for answering. but I found expandPsuedo instructions > actually happens before post-RA, like the following code showing: > your approach is a little hacky, right? : ) > > // Expand pseudo instructions before second scheduling pass. > addPass(&ExpandPostRAPseudosID); > printAndVerify("After ExpandPostRAPseudos"); > > // Run pre-sched2 passes. > if (addPreSched2()) > printAndVerify("After PreSched2 passes"); > > // Second pass scheduler. > if (getOptLevel() != CodeGenOpt::None) { > addPass(&PostRASchedulerID); > printAndVerify("After PostRAScheduler"); > } > > > secondly, psuedo instruction is kind of compiler internal representation. I > wish our instruction pair can disclose to programmer. intrinsics can do > that. > > thanks, > --lx > > > On Fri, Nov 22, 2013 at 9:45 PM, Amara Emerson <amara.emerson at arm.com> > wrote: >> >> What about describing the instruction pairs as pseudo-instructions, and >> then expanding them in a machine function pass at the pre-emit stage? >> >> >> >> Amara > > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu llvm.cs.uiuc.edu > lists.cs.uiuc.edu/mailman/listinfo/llvmdev >
Liu Xin
2013-Nov-23 14:11 UTC
[LLVMdev] prevents instruction-scheduler from interfereing instruction pair
I think this after a second. I got your point. I can define a pseudo instruction for an instr-pair and expand it after post-RA-sched. as you said, in preEmitPass. The original intrinsic can also be kept. I just convert the intrinsic to pseudo instruction in TargetLower. Thank you for your enlightening suggestion! thanks, --lx On Sat, Nov 23, 2013 at 8:37 PM, Amara Emerson <amara.emerson at gmail.com>wrote:> What I meant was to write your own expansion pass and run it after the > scheduler passes, e.g. in the pre-emit stage. > > if (addPreEmitPass()) > printAndVerify("After PreEmit passes") > > Though if it's too hacky for you then fair enough. > > Amara > > On 23 November 2013 03:17, Liu Xin <navy.xliu at gmail.com> wrote: > > Amara, > > > > first, thank you for answering. but I found expandPsuedo instructions > > actually happens before post-RA, like the following code showing: > > your approach is a little hacky, right? : ) > > > > // Expand pseudo instructions before second scheduling pass. > > addPass(&ExpandPostRAPseudosID); > > printAndVerify("After ExpandPostRAPseudos"); > > > > // Run pre-sched2 passes. > > if (addPreSched2()) > > printAndVerify("After PreSched2 passes"); > > > > // Second pass scheduler. > > if (getOptLevel() != CodeGenOpt::None) { > > addPass(&PostRASchedulerID); > > printAndVerify("After PostRAScheduler"); > > } > > > > > > secondly, psuedo instruction is kind of compiler internal > representation. I > > wish our instruction pair can disclose to programmer. intrinsics can do > > that. > > > > thanks, > > --lx > > > > > > On Fri, Nov 22, 2013 at 9:45 PM, Amara Emerson <amara.emerson at arm.com> > > wrote: > >> > >> What about describing the instruction pairs as pseudo-instructions, and > >> then expanding them in a machine function pass at the pre-emit stage? > >> > >> > >> > >> Amara > > > > > > > > _______________________________________________ > > LLVM Developers mailing list > > LLVMdev at cs.uiuc.edu llvm.cs.uiuc.edu > > lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > >-------------- next part -------------- An HTML attachment was scrubbed... URL: <lists.llvm.org/pipermail/llvm-dev/attachments/20131123/2be2da0d/attachment.html>
Reasonably Related Threads
- [LLVMdev] prevents instruction-scheduler from interfereing instruction pair
- [LLVMdev] prevents instruction-scheduler from interfereing instruction pair
- [LLVMdev] Tail Duplication Questions
- [LLVMdev] prevents instruction-scheduler from interfereing instruction pair
- [LLVMdev] Tail Duplication Questions