search for: postraschedul

hi, I have few question about breaking anti-dependence of postRAScheduler in LLVM. when I use command line "clang -target arm -mcpu=cortex-a8 -O2 -integrated-as -c test.c -o test.o" and get objdump file as follows: ldrr1, [r0,#16]----(1 str r1, [r0,#32]----(2 ldr r1, [r0,#12]----(3 str r1, [r0,#36]----(4 ldr r1, [r0,#08]----(5 str r1, [r0,#40]----(6 However,...

I am trying to understand why PostRAScheduling is done only for ARM. Is there any limitation which prevents this from being done for x86 ? Thanks, Karthik -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110111/ecdf61db/attachment.html>

Is there any specific documentation on this? Is there a point of contact for this file that I might bug? So I have an instruction that needs noops inserted and it appears that the noops are being inserted in the EmitSchedule function of the PostRAScheduler. From the loop in EmitSchedule it looks like it's inserting noops whenever SUnit is NULL. I don't see anything in the DAG that appears odd or any empty nodes, how are these NULL SUnits inserted into the Sequence? Thanks, Ryan -------------- next part -------------- An HTML attachment wa...

On Jan 11, 2011, at 2:56 PM, JG wrote: > I am trying to understand why PostRAScheduling is done only for ARM. Is there any limitation which prevents this from being done for x86 ? It's a 10% increase in overall compile time, and it does not help very much for x86. The out-of-order execution on new x86 chips hide any benefits from late scheduling. /jakob

----- Original Message ----- > > > > hi, > I have few question about breaking anti-dependence of postRAScheduler > in LLVM. > when I use command line "clang -target arm -mcpu=cortex-a8 -O2 > -integrated-as -c test.c -o test.o" > and get objdump file as follows: > ldr r1, [r0,#16]----(1 > str r1, [r0,#32]----(2 > ldr r1, [r0,#12]----(3 > str r1, [r0,#36]----(4 > ldr r1, [...

Hi, I’m facing a crash issue (--target=arm-linux-gnueabi -march=armv8-a+crc -mfloat-abi=hard) and debugging the problem, I found that an intended branch was not taken due to bad code generation after the Post RA Scheduler pass. A CMPri instruction after an INLINEASM block (which inturn contains a cmp, bne instruction) is being moved before the INLINEASM block incorrectly resulting in two

Hello, Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler I get an error that says “/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h fatal error: MipsGenRegisterInfo.inc file not found”. I’m assuming that the MipsGenRegisterInfo.inc is not yet generated when I’m trying to include it in the PostRAScheduler. Is thi...

...g pass. addPass(&ExpandPostRAPseudosID); printAndVerify("After ExpandPostRAPseudos"); // Run pre-sched2 passes. if (addPreSched2()) printAndVerify("After PreSched2 passes"); // Second pass scheduler. if (getOptLevel() != CodeGenOpt::None) { addPass(&PostRASchedulerID); printAndVerify("After PostRAScheduler"); } secondly, psuedo instruction is kind of compiler internal representation. I wish our instruction pair can disclose to programmer. intrinsics can do that. thanks, --lx On Fri, Nov 22, 2013 at 9:45 PM, Amara Emerson <amara.emers...

...pandPostRAPseudos"); > > > > // Run pre-sched2 passes. > > if (addPreSched2()) > > printAndVerify("After PreSched2 passes"); > > > > // Second pass scheduler. > > if (getOptLevel() != CodeGenOpt::None) { > > addPass(&PostRASchedulerID); > > printAndVerify("After PostRAScheduler"); > > } > > > > > > secondly, psuedo instruction is kind of compiler internal > representation. I > > wish our instruction pair can disclose to programmer. intrinsics can do > > that. >...

...ve nothing to do with the post-RA scheduler. -Jim On May 30, 2013, at 6:23 AM, Jafar J <pluck90 at hotmail.com> wrote: > Hello, > > Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler I get an error that says “/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h fatal error: MipsGenRegisterInfo.inc file not found”. I’m assuming that the MipsGenRegisterInfo.inc is not yet generated when I’m trying to include it in the PostRAScheduler. Is thi...

...ters have nothing to do with the post-RA scheduler. -Jim On May 30, 2013, at 6:23 AM, Jafar J <pluck90 at hotmail.com> wrote: Hello, Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler I get an error that says “/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h fatal error: MipsGenRegisterInfo.inc file not found”. I’m assuming that the MipsGenRegisterInfo.inc is not yet generated when I’m trying to include it in the PostRAScheduler. Is thi...

...at is there to think about in this approach? I must be missing some detail… > > Any help is appreciated, > > Jonas Paulsson Jonas, I'm sorry I forgot to respond to this. Hopefully you figured out how to debug it. I'm not sure if you're using the MachineScheduler pass or PostRAScheduler. For MachineScheduler, use -view-misched-dags and -debug-only=misched. For PostRA: -debug-only=post-RA-sched. Modifying the DAG edges is tricky to get right. But removePred() and addPred() are the basic primitives... -Andy -------------- next part -------------- An HTML attachment was scrubb...

...D); > printAndVerify("After ExpandPostRAPseudos"); > > // Run pre-sched2 passes. > if (addPreSched2()) > printAndVerify("After PreSched2 passes"); > > // Second pass scheduler. > if (getOptLevel() != CodeGenOpt::None) { > addPass(&PostRASchedulerID); > printAndVerify("After PostRAScheduler"); > } > > > secondly, psuedo instruction is kind of compiler internal representation. I > wish our instruction pair can disclose to programmer. intrinsics can do > that. > > thanks, > --lx > > > On...

...currently the only other pass we have disabled in WebAssemblyTargetMachine is MachineCopyPropagation. > Several passes (post-RA MachineLICM, StackSlotColoring) already only run if RA runs. > Everything else is running today. Currently that's ShrinkWrap, BranchFolder, ExpandPostRAPseudos, PostRAScheduler, GCMachineCodeAnalysis, MachineBlockPlacement, FuncletLayout, and StackMapLiveness. All of these run after our register coloring pass. I don’t know for the other passes, but I don’t think it makes sense to teach PrologEpilogInserter to work on virtual registers, since part of its job is to get r...

...d according to how they appear in lib/CodeGen/Passes.cpp): OptimizedRegAlloc: (run only if there is a RegAllocPass, which is not true for wasm) StackSlotColoring PostRAMachineLICM ShrinkWrap PrologEpilogInserter Machine late optimization: BranchFolderPass TailDuplicate MachineCopyPropagation PostRAScheduler ExpandPostRAPseudos ImplicitNullChecks (optional) PostMachineScheduler or PostRAScheduler GC: GCMachineCodeAnalysis GC info printer Block Placement: MachineBlockPlacement MachineBlockPlacementStats FuncletLayout StackMapLiveness LiveDebugValues All of the pre-regalloc passes (and analyses) w...

Hi, I am trying to add Hazard scheduling nodes after buildSchedGraph(), with a scheduler derived from ScheduleDAGInstrs. I get weird errors, so I wonder what I am doing wrong? What I am doing right now is: I have a created MI with opcode HAZARD that does not have parent, and I greate a SUnit(HazardMI). I use this one HazardMI for all hazard nodes. I remove all edges using removePred. I insert

...Node -> pred. What is there to think about in this approach? I must be missing some detail... Any help is appreciated, Jonas Paulsson Jonas, I'm sorry I forgot to respond to this. Hopefully you figured out how to debug it. I'm not sure if you're using the MachineScheduler pass or PostRAScheduler. For MachineScheduler, use -view-misched-dags and -debug-only=misched. For PostRA: -debug-only=post-RA-sched. Modifying the DAG edges is tricky to get right. But removePred() and addPred() are the basic primitives... -Andy -------------- next part -------------- An HTML attachment was scrubbe...

...duler. > > -Jim > > On May 30, 2013, at 6:23 AM, Jafar J <pluck90 at hotmail.com> wrote: > >> Hello, >> >> Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler I get an error that says “/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h fatal error: MipsGenRegisterInfo.inc file not found”. I’m assuming that the MipsGenRegisterInfo.inc is not yet generated when I’m trying to include it in the PostRAScheduler. Is thi...

...> > OptimizedRegAlloc: (run only if there is a RegAllocPass, which is not true > for wasm) > StackSlotColoring > PostRAMachineLICM > ShrinkWrap > PrologEpilogInserter > Machine late optimization: > BranchFolderPass > TailDuplicate > MachineCopyPropagation > PostRAScheduler > ExpandPostRAPseudos > ImplicitNullChecks (optional) > PostMachineScheduler or PostRAScheduler > GC: > GCMachineCodeAnalysis > GC info printer > Block Placement: > MachineBlockPlacement > MachineBlockPlacementStats > FuncletLayout > StackMapLiveness > Live...

...e nothing to do with the post-RA scheduler. -Jim On May 30, 2013, at 6:23 AM, Jafar J <pluck90 at hotmail.com> wrote: Hello, Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler I get an error that says “/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h fatal error: MipsGenRegisterInfo.inc file not found”. I’m assuming that the MipsGenRegisterInfo.inc is not yet generated when I’m trying to include it in the PostRAScheduler. Is thi...