search for: amara

Folks, For some reason, all new phabricator diffs are automatically including Amara, which is probably a bit annoying for him, but pointless. I believe it happens because his name is the first in the alphabetical order. Can someone have a look at what's going on? cheers, --renato

On 9 February 2017 at 17:31, Amara Emerson <amara.emerson at gmail.com> wrote: > Ping. Does anyone else have thoughts on this? Hi Amara, It seems the people who replied in this thread are mostly in sync with the proposal, why don't you push a review in phab, and let's take this to the next level? cheers, --renato

Amara, first, thank you for answering. but I found expandPsuedo instructions actually happens before post-RA, like the following code showing: your approach is a little hacky, right? : ) // Expand pseudo instructions before second scheduling pass. addPass(&ExpandPostRAPseudosID); printAndVerif...

...do instruction for an instr-pair and expand it after post-RA-sched. as you said, in preEmitPass. The original intrinsic can also be kept. I just convert the intrinsic to pseudo instruction in TargetLower. Thank you for your enlightening suggestion! thanks, --lx On Sat, Nov 23, 2013 at 8:37 PM, Amara Emerson <amara.emerson at gmail.com>wrote: > What I meant was to write your own expansion pass and run it after the > scheduler passes, e.g. in the pre-emit stage. > > if (addPreEmitPass()) > printAndVerify("After PreEmit passes") > > Though if it's too...

What I meant was to write your own expansion pass and run it after the scheduler passes, e.g. in the pre-emit stage. > if (addPreEmitPass()) printAndVerify("After PreEmit passes") Though if it's too hacky for you then fair enough. Amara On 23 November 2013 03:17, Liu Xin <navy.xliu at gmail.com> wrote: > Amara, > > first, thank you for answering. but I found expandPsuedo instructions > actually happens before post-RA, like the following code showing: > your approach is a little hacky, right? : ) > > //...

...ctorize early exit loops by using speculative (first-faulting) loads, which essentially give a predicate of the lanes loaded successfully. For uncounted loops with these special loads, the loop predicate tests can be done using a 'ptest' instruction, checking if the last element is active. Amara On 3 February 2017 at 10:15, Simon Pilgrim <llvm-dev at redking.me.uk> wrote: > >> On 2 Feb 2017, at 01:06, Amara Emerson <amara.emerson at gmail.com> wrote: >>> >>> What stops us from doing so with intrinsics is just the knowledge, so >>> we trade c...

FYI all: the patch to enable it is available to review here: https://reviews.llvm.org/D41362 Thanks, Amara > On Dec 18, 2017, at 5:44 PM, Amara Emerson via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Ok. We’ll look at what we can do to further stress test it in the next two months, additional suggestions from the community is welcome. Patch should be incoming to enable it later tod...

...into. It has some similarities with forcing fallbacks, but uses a different mechanism to do so to preserve the abort behavior. It therefore requires that every GISel pass needs to explicitly check whether the GISel selector is being requested rather than just using the FailedISel property. Cheers, Amara > On May 5, 2020, at 6:56 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > Hi Amara, > > I’ve done that internally for testing purposes and basically the existing GISel pipeline with fallbacks just did what I wanted. > In other words, I always used the GISel pipel...

...t; > Do we want GCC compatibility? > > > > Regards, > > > > Bernie > > > > > > *From:* cfe-dev-bounces at cs.uiuc.edu [mailto:cfe-dev-bounces at cs.uiuc.edu] *On > Behalf Of *Eric Christopher > *Sent:* 07 January 2014 21:37 > *To:* Renato Golin; Amara Emerson; Clang Dev; LLVM Dev > *Subject:* Re: [cfe-dev] [LLVMdev] AArch64 Clang CLI interface proposal > > > > Parsing the arch string is a bit icky, but I don't really have too much of > a problem with it - and it's better than -mcpu so... > > > > -eric > &...

Unless there are still open issues with your patch, or our internal bots point to problems, I think time has come to flip the switch. Thanks Gerolf > On Dec 18, 2017, at 11:14 AM, Amara Emerson via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > FYI all: the patch to enable it is available to review here: https://reviews.llvm.org/D41362 <https://reviews.llvm.org/D41362> > > Thanks, > Amara > >> On Dec 18, 2017, at 5:44 PM, Amara Emerson via...

...t merb using script/merb and stdout/stderr look like this: $ script/merb Merb started with these options: --- :exception_details: true :reloader: true :session_secret_key: .6393 :mongrel_x_sendfile: true :reloader_time: 0.5 :cache_templates: false :merb_root: /home/francois/src/florian-opsdb/trunk/amara :use_mutex: true :host: 127.0.0.1 :session_id_cookie_only: true :environment: development :port: "4000" :query_string_whitelist: [] Started merb_init.rb ... Connecting to database... Thu, 13 Dec 2007 03:22:38 GMT: loading gem ''merb_activerecord'' from config/dependenci...

Parsing the arch string is a bit icky, but I don't really have too much of a problem with it - and it's better than -mcpu so... -eric On Tue Jan 07 2014 at 9:23:43 AM, Renato Golin <renato.golin at linaro.org> wrote: > On 7 January 2014 17:05, Amara Emerson <amara.emerson at arm.com> wrote: > > We plan on implementing this interface for AArch64 Clang in future, and > completely dropping the current support for -mfpu. This means that -march > will become the preferred way to specify the target CPU/architecture. > > >...

...cularly be problematic for us to do it at the IR level. The existing TLI hooks to specify how certain memcpy calls should be lowered doesn’t have anything too SelectionDAG specific, and an IR lowering pass could be shared in future between SDAG and GISel. Does anyone see issues with this? Thanks, Amara

...flipping the switch. At this point, I’d aim to flip the switch shortly after the creation of the 6.0.0 release branch, so that GlobalISel can harden a bit more enabled-by-default on trunk before it goes into an LLVM release (presumably 7.0.0 then). Thanks, Kristof > On 11 Dec 2017, at 17:08, Amara Emerson <aemerson at apple.com> wrote: > > As of r320388 we’ve either fixed the blocker bugs or disabled big-endian on GISel, falling back to SDAG. Fixing at least one of the big-endian issues will need use to change the way we handle aggregates, which will take a bit longer (it’s next...

I am not using llvm tools, but sources and directly calling into relevant LLVM classes and methods. Thanks, Daman On 23/06/14 4:11 pm, "Amara Emerson" <amara.emerson at gmail.com> wrote: >Hi Damanjit, > >I assume you're trying to use the tools like llvm-mc, in which case >you can use the -mattr=+vfpv3 flag to enable it. This applies to other >subtarget features defined in ARM.td as well. > >Cheers, &g...

...c %s -o %t1 2> %t2; echo "ok" +@ RUN: cat %t2 | FileCheck %s Clang tests shouldn't be in the LLVM regression suite. Use llvm-mc instead for assembling. I'm not very familiar with the code around the asm parser, so I expect more detailed comments from others to follow. Cheers, Amara

Hi Amara, Thanks for your suggestions. I have made the changes you suggested and added a new test to check that we print an error when parsing a non-ldr mnemonic with an operand containing `=`. The updated patch is attached. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by T...

Thanks Amara so much for the info! One more question: what do people usually do if they want to generate vectorized code for some existing c/c++ code? Do they usually do C/C++ source level transformation, or do at LLVM's IR level? I know clang supports auto vectorizations, such as loop vectorization and S...

Hi Amara, My reasons for preferring the switch to happen after the release branch is based on the following observations: * As far as I can see, the projects and products following top-of-trunk tend to test much more extensively than the testing that happens for llvm.org<http://llvm.org> release...

...work last year to refine the semantics after some discussion. Are we at the point where we can drop the “experimental” from the name? IMO all target should begin to transition to using these as the preferred representation for reductions. But for now, I’m only proposing the naming change. Cheers, Amara