Displaying 8 results from an estimated 8 matches for "addpresched2".
2013 Nov 23
2
[LLVMdev] prevents instruction-scheduler from interfereing instruction pair
...ually happens before post-RA, like the following code showing:
your approach is a little hacky, right? : )
// Expand pseudo instructions before second scheduling pass.
addPass(&ExpandPostRAPseudosID);
printAndVerify("After ExpandPostRAPseudos");
// Run pre-sched2 passes.
if (addPreSched2())
printAndVerify("After PreSched2 passes");
// Second pass scheduler.
if (getOptLevel() != CodeGenOpt::None) {
addPass(&PostRASchedulerID);
printAndVerify("After PostRAScheduler");
}
secondly, psuedo instruction is kind of compiler internal representati...
2013 Nov 23
0
[LLVMdev] prevents instruction-scheduler from interfereing instruction pair
...following code showing:
> your approach is a little hacky, right? : )
>
> // Expand pseudo instructions before second scheduling pass.
> addPass(&ExpandPostRAPseudosID);
> printAndVerify("After ExpandPostRAPseudos");
>
> // Run pre-sched2 passes.
> if (addPreSched2())
> printAndVerify("After PreSched2 passes");
>
> // Second pass scheduler.
> if (getOptLevel() != CodeGenOpt::None) {
> addPass(&PostRASchedulerID);
> printAndVerify("After PostRAScheduler");
> }
>
>
> secondly, psuedo instru...
2013 Nov 23
1
[LLVMdev] prevents instruction-scheduler from interfereing instruction pair
...approach is a little hacky, right? : )
> >
> > // Expand pseudo instructions before second scheduling pass.
> > addPass(&ExpandPostRAPseudosID);
> > printAndVerify("After ExpandPostRAPseudos");
> >
> > // Run pre-sched2 passes.
> > if (addPreSched2())
> > printAndVerify("After PreSched2 passes");
> >
> > // Second pass scheduler.
> > if (getOptLevel() != CodeGenOpt::None) {
> > addPass(&PostRASchedulerID);
> > printAndVerify("After PostRAScheduler");
> > }
>...
2015 Oct 22
2
add intrinsic function support for customized backend
Hi, All,
I want to add one intrinsic function for my particular backend. Let's say
the intrinsic function is named "foo" which takes two i32 inputs and has
one i32 output.
First, I add this line "def int_foo : Intrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty], [IntrReadArgMem]>;" in
/include/llvm/IR/Intrinsics.td.
Then, in my target/InstrInfo.td, I'm supposed
2019 Mar 02
2
Support for out-of-tree backend passes?
Hi all,
I've been doing some LLVM development recently, as was curious about
the status/feasibility of allowing developers to write out-of-tree
back-end passes (e.g. `MachineFunctionPass`es) in a matter similar
to middle-end passes.
From the limited resources I can find online[1][2][3], LLVM currently
doesn't support building back-end passes outside of the source tree.
Could anybody more
2015 Oct 22
2
add intrinsic function support for customized backend
...ot be altered
> afterwards.
>
> Finally, it the two previous passes are not suitable for a particular
> reason, other more generic ways exist. Simply create a new
> MachineFunctionPass and call it when you need it. For example from:
> - addPreRegAlloc
> - addPostRegAlloc
> - addPreSched2
> - addPreEmitPass
>
> I don't have a big LLVM background but thus are my findings when I was
> playing with the middle-end/back-end some time ago.
>
> Regards,
> Gaël
>
>
> _______________________________________________
> LLVM Developers mailing list
> llvm...
2017 Mar 07
2
Specifying conditional blocks for the back end
Hello.
Because I experience optimizations (DCE, OoO schedule) which mess the correct
semantics of the list of instructions lowered in ISelLowering from the VSELECT LLVM
instruction, and these bad transformations happen even before scheduling, at later I-sel
subpasses, I try to fix this problem by lowering VSELECT to only one pseudo-instruction
and LATER translate it to a list of
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
...GPUTargetMachine &getAMDGPUTargetMachine() const {
> + return getTM<AMDGPUTargetMachine>();
> + }
> +
> + virtual bool addPreISel();
> + virtual bool addInstSelector();
> + virtual bool addPreRegAlloc();
> + virtual bool addPostRegAlloc();
> + virtual bool addPreSched2();
> + virtual bool addPreEmitPass();
> +};
> +} // End of anonymous namespace
> +
> +TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
> + return new AMDGPUPassConfig(this, PM);
> +}
> +
> +bool
> +AMDGPUPassConfig::addPreISel()
>...