hi, Hal
Thanks for your reply. my test case is as follows:
//test.c
struct AAA {
int a;
int b;
int c;
int d;
int e;
int f;
}arr;
__attribute__((__noinline__))
int test() {
arr.a = arr.d;
arr.b = arr.e;
arr.c = arr.f;
return 0;
}
//end test.c
At 2013-10-09 21:32:55,"Hal Finkel" <hfinkel at anl.gov>
wrote:>----- Original Message -----
>>
>>
>>
>> hi,
>> I have few question about breaking anti-dependence of postRAScheduler
>> in LLVM.
>> when I use command line "clang -target arm -mcpu=cortex-a8 -O2
>> -integrated-as -c test.c -o test.o"
>> and get objdump file as follows:
>> ldr r1, [r0,#16]----(1
>> str r1, [r0,#32]----(2
>> ldr r1, [r0,#12]----(3
>> str r1, [r0,#36]----(4
>> ldr r1, [r0,#08]----(5 !
>> str r1, [r0,#40]----(6
>> However, I expect that instruction pairs (1,2), (3,4) and (5,6) use
>> different registers after postRAScheduler pass.
>> Then, I find that postRAScheduler only handle anti-dependence mode
>> after debug LLVM source code.
>
>I'm not familiar with ARM, but I use full anti-dependency breaking on
PowerPC with the postRAScheduler, and it certainly has an effect in a Release
build. Can you please be more specific about what you've tried/found?
my clang version is SVN3.4. I use the following command line
"$ clang -emit-llvm -S -O2 test.c -o test.ll "
"$ llc -march=ppc32 -mcpu=970 -O2 test.ll"
then open test.s file:
la 3, arr at l(4)
lwz 5, 12(3)
stw 5, arr at l(4)
lwz 4, 16(3)
stw 4, 4(3)
lwz 4, 20(3)
stw 4, 8(3)
maybe it's better to break anti-dependence on arm. But the latter two
instruction pairs can be broken dependence.
And which anti mode do you used on PowerPC?
TargetSubtargetInfo::ANTIDEP_CRITICAL or
TargetSubtargetInfo::ANTIDEP_ALL?
I set anti mode as ANTIDEP_CRITICAL .
as test.s shows, the registers of the last two instruction pairs can be renamed.
Register renaming depend on the dependence mode{data, anti, output, order} which
set by data flow in addPhysRegDeps function of ScheduleDAGInstrs.cpp . When I
debug addPhysRegDeps function, I find that it analyse every instruction's
operand and set relative dependence mode. It's reasonable.
However, it is unable to handle instruction pairs like (3,4) and (5,6), because
it treats every instruction pair as data dependence mode. I know data mode is
correct.
but, instructions 4 and 5 can be treat as anti dependence mode(Maybe it is not
correct).
Moreover, can instructions pair (3,4) together set anti deps mode with
(5,6)?>
> -Hal
>
>> More while I use gcc to compile test.c and get expected result.
>> Is it this compiler's drawbacks? Is any developer doing this
>> function?
>> it's my pleasure if any suggestion.
>> Thanks.
>>
>>
>> _______________________________________________
>> LLVM Developers mailing list
>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>
>
>--
>Hal Finkel
>Assistant Computational Scientist
>Leadership Computing Facility
>Argonne National Laboratory
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