search for: addphysregdep

...; C: %vreg6<def> = FOO %vreg3<kill>, %F_OVERFLOW<imp-def> ... When constructing a MISched DAG, I expect to see output dependencies (A -> C) and (B -> C). I assert that output dependency (A -> B) is spurious because F_OVERFLOW is dead at B. Indeed, ScheduleDAGInstrs::addPhysRegDeps already includes a test for this case (if MO.isDead()), confirming that the developer intended to omit output dependencies on dead registers. However, the LiveVariables pass clears the isDead flag from all operands that reference F_OVERFLOW and does not reset those flags. Without this informat...

----- Original Message ----- > > > > hi, > I have few question about breaking anti-dependence of postRAScheduler > in LLVM. > when I use command line "clang -target arm -mcpu=cortex-a8 -O2 > -integrated-as -c test.c -o test.o" > and get objdump file as follows: > ldr r1, [r0,#16]----(1 > str r1, [r0,#32]----(2 > ldr r1, [r0,#12]----(3 > str r1,

hi, I have few question about breaking anti-dependence of postRAScheduler in LLVM. when I use command line "clang -target arm -mcpu=cortex-a8 -O2 -integrated-as -c test.c -o test.o" and get objdump file as follows: ldrr1, [r0,#16]----(1 str r1, [r0,#32]----(2 ldr r1, [r0,#12]----(3 str r1, [r0,#36]----(4 ldr r1, [r0,#08]----(5 str r1, [r0,#40]----(6 However, I expect that instruction

Hello, The ScheduleDAGInstrs::buildSchedGraph() function creates def/uses lists by iterating over all instruction operands and calls addPhysRegDeps() if used post-RA (line ~770 ff.). If an operand is a def, the uses of that registers are cleared (ScheduleDAGInstrs.cpp:333: Uses.eraseAll(Reg); ). As a consequence, if an instruction has an explicit use of a register and an implicit def of the same register, the implicit def causes the use to...

...this example. Cheers, Stefan On 2014-02-25 17:35, Tom Stellard wrote: > On Tue, Feb 25, 2014 at 04:38:46PM +0100, Stefan Hepp wrote: >> Hello, >> >> The ScheduleDAGInstrs::buildSchedGraph() function creates def/uses lists by iterating over all instruction operands and calls addPhysRegDeps() if used post-RA (line ~770 ff.). If an operand is a def, the uses of that registers are cleared (ScheduleDAGInstrs.cpp:333: Uses.eraseAll(Reg); ). >> >> As a consequence, if an instruction has an explicit use of a register and an implicit def of the same register, the implicit def c...

Hello, My out-of-tree target features some high latency instructions (let's call them FXLV). When an FXLV issues, it reserves its destination register and execution continues; if a subsequent instruction attempts to read or write that register, the pipline will stall until the FXLV completes. I have attempted to encode this constraint in the machine scheduler (excerpt at bottom of email).