search for: lwz

..., > but your litmus test: > > > PPC WRCnf+addrs > > "" > > { > > 0:r2=x; 0:r3=y; > > 1:r2=x; 1:r3=y; > > 2:r2=x; 2:r3=y; > > c=a; d=b; x=c; y=d; > > } > > P0 | P1 | P2 ; > > stw r3,0(r2) | lwz r8,0(r2) | lwz r8,0(r3) ; > > | stw r2,0(r3) | lwz r9,0(r8) ; > > exists > > (1:r8=y /\ 2:r8=x /\ 2:r9=c) > > Seems to be missing the address dependency on P1. You are quite correct! How about the following? As before, both herd and ppcmem say that the...

..., > but your litmus test: > > > PPC WRCnf+addrs > > "" > > { > > 0:r2=x; 0:r3=y; > > 1:r2=x; 1:r3=y; > > 2:r2=x; 2:r3=y; > > c=a; d=b; x=c; y=d; > > } > > P0 | P1 | P2 ; > > stw r3,0(r2) | lwz r8,0(r2) | lwz r8,0(r3) ; > > | stw r2,0(r3) | lwz r9,0(r8) ; > > exists > > (1:r8=y /\ 2:r8=x /\ 2:r9=c) > > Seems to be missing the address dependency on P1. You are quite correct! How about the following? As before, both herd and ppcmem say that the...

...on openSUSE 13.1 PPC64. Total of 3 failures which seems to be due the same problem (the value in brackets is the time counter from the build system): [ 3468s] /home/abuild/rpmbuild/BUILD/llvm/test/CodeGen/PowerPC/ppc32-vacopy.ll:21:10: error: expected string not found in input [ 3468s] ; CHECK: lwz [[REG3:[0-9]+]], {{.*}} [ 3468s] ^ [ 3468s] <stdin>:15:2: note: scanning from here [ 3468s] stw 5, 16(1) [ 3468s] ^ [ 3468s] <stdin>:17:3: note: possible intended match here [ 3468s] stw 4, 4(7) [ 3468s] ^ [ 3467s] /home/abuild/rpmbuild/BUILD/llvm/test/CodeGen/PowerPC/ano...

...ot; > > > > { > > > > 0:r2=x; 0:r3=y; > > > > 1:r2=x; 1:r3=y; > > > > 2:r2=x; 2:r3=y; > > > > c=a; d=b; x=c; y=d; > > > > } > > > > P0 | P1 | P2 ; > > > > stw r3,0(r2) | lwz r8,0(r2) | lwz r8,0(r3) ; > > > > | stw r2,0(r3) | lwz r9,0(r8) ; > > > > exists > > > > (1:r8=y /\ 2:r8=x /\ 2:r9=c) > > > > > > Seems to be missing the address dependency on P1. > > > > You are quite correct! H...

...ot; > > > > { > > > > 0:r2=x; 0:r3=y; > > > > 1:r2=x; 1:r3=y; > > > > 2:r2=x; 2:r3=y; > > > > c=a; d=b; x=c; y=d; > > > > } > > > > P0 | P1 | P2 ; > > > > stw r3,0(r2) | lwz r8,0(r2) | lwz r8,0(r3) ; > > > > | stw r2,0(r3) | lwz r9,0(r8) ; > > > > exists > > > > (1:r8=y /\ 2:r8=x /\ 2:r9=c) > > > > > > Seems to be missing the address dependency on P1. > > > > You are quite correct! H...

...e benefits of fake dependencies. Why do you ask? ;-) ------------------------------------------------------------------------ PPC WRCnf+addrs "" { 0:r2=x; 0:r3=y; 1:r2=x; 1:r3=y; 2:r2=x; 2:r3=y; c=a; d=b; x=c; y=d; } P0 | P1 | P2 ; stw r3,0(r2) | lwz r8,0(r2) | lwz r8,0(r3) ; | stw r2,0(r3) | lwz r9,0(r8) ; exists (1:r8=y /\ 2:r8=x /\ 2:r9=c)

...e benefits of fake dependencies. Why do you ask? ;-) ------------------------------------------------------------------------ PPC WRCnf+addrs "" { 0:r2=x; 0:r3=y; 1:r2=x; 1:r3=y; 2:r2=x; 2:r3=y; c=a; d=b; x=c; y=d; } P0 | P1 | P2 ; stw r3,0(r2) | lwz r8,0(r2) | lwz r8,0(r3) ; | stw r2,0(r3) | lwz r9,0(r8) ; exists (1:r8=y /\ 2:r8=x /\ 2:r9=c)

...hich seems to be due the same problem (the value > in brackets is the time counter from the build system): > > > > > [ 3468s] > /home/abuild/rpmbuild/BUILD/llvm/test/CodeGen/PowerPC/ppc32-vacopy.ll:21:10: > error: expected string not found in input > [ 3468s] ; CHECK: lwz [[REG3:[0-9]+]], {{.*}} > [ 3468s] ^ > [ 3468s] <stdin>:15:2: note: scanning from here > [ 3468s] stw 5, 16(1) > [ 3468s] ^ > [ 3468s] <stdin>:17:3: note: possible intended match here > [ 3468s] stw 4, 4(7) > [ 3468s] ^ > > > > [ 3467s] > /home/abu...

...e__ ((__vector_size__(16))); interval_t add(interval_t a, interval_t b) { return a + b; } to the following (under gcc version 4.0.1 (Apple Inc. build 5484)) _add: lfd f0,80(r1) lfd f12,64(r1) lfd f13,72(r1) fadd f12,f12,f0 lfd f0,88(r1) fadd f13,f13,f0 stfd f12,-32(r1) stfd f13,-24(r1) lwz r3,-32(r1) lwz r4,-28(r1) lwz r5,-24(r1) lwz r6,-20(r1) blr which means that GCC is choosing to pass the doubles on the stack instead of in registers and so I cannot mix the LLVM code with the GCC code. Now, I realize that __vector_size__ is a GCC extension and so they're allowed to...

...stw 3, 44(1) stw 3, 44(1) # InlineAsm Start --> isync # InlineAsm End lwz 3, 44(1) lwz 3, 44(1) cmpwi 0, 3, -1 cmpwi 0, 3, -1 I would like to insert Code (like the isync) in the asm output of the llc. What is the best way, or easiest to do this. llc -filetype=asm -march=ppc32 -o=test.s test.bc...

...PPC WRCnf+addrs > > > "" > > > { > > > 0:r2=x; 0:r3=y; > > > 1:r2=x; 1:r3=y; > > > 2:r2=x; 2:r3=y; > > > c=a; d=b; x=c; y=d; > > > } > > > P0 | P1 | P2 ; > > > stw r3,0(r2) | lwz r8,0(r2) | lwz r8,0(r3) ; > > > | stw r2,0(r3) | lwz r9,0(r8) ; > > > exists > > > (1:r8=y /\ 2:r8=x /\ 2:r9=c) > > > > Seems to be missing the address dependency on P1. > > You are quite correct! How about the following? I think th...

...g at 1122 Morphed node: 0x3eaaa58: i32 = ADD 0x3ea7648, 0x3eaa950 [ORD=7] ISEL: Match complete! ISEL: Starting pattern match on root node: 0x3ea9288: i32,ch = load 0x3e7e2f0, 0x3eac3b0, 0x3ea45e0<LD4[%b+12]> [ORD=6] [ID=27] Initial Opcode index to 122 Morphed node: 0x3ea9288: i32,ch = LWZ 0x3ea4b08, 0x3ea8d60, 0x3e7e2f0<Mem:LD4[%b+12]> [ORD=6] ISEL: Match complete! ISEL: Starting pattern match on root node: 0x3ea7540: i32,ch = load 0x3e7e2f0, 0x3eaae78, 0x3ea45e0<LD4[%a+12]> [ORD=5] [ID=26] Initial Opcode index to 122 Morphed node: 0x3ea7540: i32,ch = LWZ 0x3eac3b0...

I've been playing around with llvm lately and I was wondering something about the bitcode instructions for basic arithmetic. Is there any plan to provide instructions that perform widening multiply, or add with carry? It might be written as: mulw i32 %lhs %rhs -> i64 ; widening multiply addw i32 %lhs %rhs -> i33 ; widening add addc i32 %lhs, i32 %rhs, i1 %c -> i33 ; add with carry

...; > { > 0:r1=1; 0:r2=u; 0:r3=v; 0:r4=x; 0:r5=y; 0:r6=z; > 1:r1=1; 1:r2=u; 1:r3=v; 1:r4=x; 1:r5=y; 1:r6=z; > 2:r1=1; 2:r2=u; 2:r3=v; 2:r4=x; 2:r5=y; 2:r6=z; > 3:r1=1; 3:r2=u; 3:r3=v; 3:r4=x; 3:r5=y; 3:r6=z; > } > P0 | P1 | P2 | P3 ; > lwz r9,0(r4) | lwz r9,0(r5) | lwz r9,0(r6) | stw r1,0(r3) ; > lwsync | lwsync | lwsync | sync ; > stw r1,0(r2) | lwz r8,0(r3) | stw r1,0(r7) | lwz r9,0(r2) ; > lwsync | lwz r7,0(r2) | | ; > stw r1,0(r5) | lwsync |...

...; > { > 0:r1=1; 0:r2=u; 0:r3=v; 0:r4=x; 0:r5=y; 0:r6=z; > 1:r1=1; 1:r2=u; 1:r3=v; 1:r4=x; 1:r5=y; 1:r6=z; > 2:r1=1; 2:r2=u; 2:r3=v; 2:r4=x; 2:r5=y; 2:r6=z; > 3:r1=1; 3:r2=u; 3:r3=v; 3:r4=x; 3:r5=y; 3:r6=z; > } > P0 | P1 | P2 | P3 ; > lwz r9,0(r4) | lwz r9,0(r5) | lwz r9,0(r6) | stw r1,0(r3) ; > lwsync | lwsync | lwsync | sync ; > stw r1,0(r2) | lwz r8,0(r3) | stw r1,0(r7) | lwz r9,0(r2) ; > lwsync | lwz r7,0(r2) | | ; > stw r1,0(r5) | lwsync |...

On Thu, Jan 14, 2016 at 01:29:13PM -0800, Paul E. McKenney wrote: > So smp_mb() provides transitivity, as do pairs of smp_store_release() > and smp_read_acquire(), But they provide different grades of transitivity, which is where all the confusion lays. smp_mb() is strongly/globally transitive, all CPUs will agree on the order. Whereas the RCpc release+acquire is weakly so, only the two

On Thu, Jan 14, 2016 at 01:29:13PM -0800, Paul E. McKenney wrote: > So smp_mb() provides transitivity, as do pairs of smp_store_release() > and smp_read_acquire(), But they provide different grades of transitivity, which is where all the confusion lays. smp_mb() is strongly/globally transitive, all CPUs will agree on the order. Whereas the RCpc release+acquire is weakly so, only the two

...------ PPC local-transitive "" { 0:r1=1; 0:r2=u; 0:r3=v; 0:r4=x; 0:r5=y; 0:r6=z; 1:r1=1; 1:r2=u; 1:r3=v; 1:r4=x; 1:r5=y; 1:r6=z; 2:r1=1; 2:r2=u; 2:r3=v; 2:r4=x; 2:r5=y; 2:r6=z; 3:r1=1; 3:r2=u; 3:r3=v; 3:r4=x; 3:r5=y; 3:r6=z; } P0 | P1 | P2 | P3 ; lwz r9,0(r4) | lwz r9,0(r5) | lwz r9,0(r6) | stw r1,0(r3) ; lwsync | lwsync | lwsync | sync ; stw r1,0(r2) | lwz r8,0(r3) | stw r1,0(r7) | lwz r9,0(r2) ; lwsync | lwz r7,0(r2) | | ; stw r1,0(r5) | lwsync | | ;...

...allowed by herd. > > > > *) > > > > { > > > > 0:r1=x; 0:r2=y; 0:r3=z; > > > > 1:r1=x; 1:r2=y; 1:r3=z; 1:r4=1; > > > > 2:r1=x; 2:r2=y; 2:r3=z; 2:r4=1; 2:r5=2; > > > > } > > > > P0 | P1 | P2 ; > > > > lwz r6,0(r1) | stw r4,0(r2) | stw r5,0(r3) ; > > > > xor r7,r6,r6 | lwsync | lwsync ; > > > > lwzx r7,r7,r2 | stw r4,0(r3) | stw r4,0(r1) ; > > > > lwz r8,0(r3) | | ; > > > > > > > > exists > > > > (z=2 /\ 0:r6=1 /\ 0:r7=0 /\...

...allowed by herd. > > > > *) > > > > { > > > > 0:r1=x; 0:r2=y; 0:r3=z; > > > > 1:r1=x; 1:r2=y; 1:r3=z; 1:r4=1; > > > > 2:r1=x; 2:r2=y; 2:r3=z; 2:r4=1; 2:r5=2; > > > > } > > > > P0 | P1 | P2 ; > > > > lwz r6,0(r1) | stw r4,0(r2) | stw r5,0(r3) ; > > > > xor r7,r6,r6 | lwsync | lwsync ; > > > > lwzx r7,r7,r2 | stw r4,0(r3) | stw r4,0(r1) ; > > > > lwz r8,0(r3) | | ; > > > > > > > > exists > > > > (z=2 /\ 0:r6=1 /\ 0:r7=0 /\...