Hi, For the synthesis backend which translate to VHDL or Verilog, I don't know if I will use LLVM. It will depend on how easy it is to play with concurrent statements with LLVM. For the simulation I will use LLVM because I can anyways artificially make the compiled code sequencial. It would allow me to benefit from all the nice things from LLVM like existing optimisations. I have never used LLVM, I just read a litlle the documentation and the tutorial. Cheers, Jonas Le 30. 08. 13 11:24, Óscar Fuentes a écrit :> Jonas Baggett<jonasb at tranquille.ch> writes: > >> What are your feedbacks ? > Hello Jonas, > > How is that related to LLVM? I see no references to LLVM on your > announcement nor on your document.
If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools). Starting from comparisons to VHDL and Verilog is like designing a new high-level programming language today that is designed to be a better high-level programming language that is supposed to provide better rapid development support than Fortran 77 and C89. David On 30 Aug 2013, at 10:43, Jonas Baggett <jonasb at tranquille.ch> wrote:> Hi, > > For the synthesis backend which translate to VHDL or Verilog, I don't know if I will use LLVM. It will depend on how easy it is to play with concurrent statements with LLVM. For the simulation I will use LLVM because I can anyways artificially make the compiled code sequencial. It would allow me to benefit from all the nice things from LLVM like existing optimisations. I have never used LLVM, I just read a litlle the documentation and the tutorial. > > Cheers, > Jonas > > > Le 30. 08. 13 11:24, Óscar Fuentes a écrit : >> Jonas Baggett<jonasb at tranquille.ch> writes: >> >>> What are your feedbacks ? >> Hello Jonas, >> >> How is that related to LLVM? I see no references to LLVM on your >> announcement nor on your document. > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
Jonas Baggett <jonasb at tranquille.ch> writes: [snip] Okay. Please note that this mailing list is exclusively for discussing topics about LLVM development and usage, not a general forum for programming languages, so you will get little feedback here (and if there is any, it will be quickly stopped by the moderators.)
Most of the existing HDLs are bad (one way or another), after a stint on the SystemVerilog committee I decided it could be done better in C++ and the missing piece in C++ is just the threading model. The current approach to threads in C++ is based on the C approach of using a function as the base of the thread which immediately gets you into trouble by creating a stack you have to manage, HDLs base threads on on class instances that only need a stack to handle method calls. VHDL and Verilog are 1980s technology, but none of the more recent stuff is much better - generally the abstractions used are the wrong ones. I'd skip the HDLs and look at what's happening in software-defined-networking for inspiration. Kev. http://parallel.cc On 08/30/2013 02:59 AM, David Chisnall wrote:> If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools). Starting from comparisons to VHDL and Verilog is like designing a new high-level programming language today that is designed to be a better high-level programming language that is supposed to provide better rapid development support than Fortran 77 and C89. > > David > > On 30 Aug 2013, at 10:43, Jonas Baggett <jonasb at tranquille.ch> wrote: > >> Hi, >> >> For the synthesis backend which translate to VHDL or Verilog, I don't know if I will use LLVM. It will depend on how easy it is to play with concurrent statements with LLVM. For the simulation I will use LLVM because I can anyways artificially make the compiled code sequencial. It would allow me to benefit from all the nice things from LLVM like existing optimisations. I have never used LLVM, I just read a litlle the documentation and the tutorial. >> >> Cheers, >> Jonas >> >> >> Le 30. 08. 13 11:24, Óscar Fuentes a écrit : >>> Jonas Baggett<jonasb at tranquille.ch> writes: >>> >>>> What are your feedbacks ? >>> Hello Jonas, >>> >>> How is that related to LLVM? I see no references to LLVM on your >>> announcement nor on your document. >>
Le 30. 08. 13 11:59, David Chisnall a écrit :> If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools).That's a good idea before I go too far , and I think that MyHDL worths a look too. For Symbolics Processor Designer, I tried to find that in google, but I am not sure that I found what you were speaking about. Do you have a link ? I just discover that this mailing list is for speaking about LLVM developpement and usage only, so for all non LLVM related discussions, go to http://www.velocityreviews.com/forums/t964068-reflexions-about-a-new-hdl-language.html. Cheers, Jonas